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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dautoidle.txt1 Binding for Texas Instruments autoidle clock.
5 and a configuration bit setting. Autoidle clock is never an individual
7 or fixed-factor.
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - reg : offset for the register controlling the autoidle
13 - ti,autoidle-shift : bit shift of the autoidle enable bit
14 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
18 #clock-cells = <0>;
19 compatible = "ti,divider-clock";
21 ti,max-div = <31>;
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H A Dfixed-factor-clock.txt3 This binding uses the common clock binding[1], and also uses the autoidle
4 support from TI autoidle clock [2].
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7 [2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
10 - compatible : shall be "ti,fixed-factor-clock".
11 - #clock-cells : from common clock binding; shall be set to 0.
12 - ti,clock-div: fixed divider.
13 - ti,clock-mult: fixed multiplier.
14 - clocks: parent clock.
17 - clock-output-names : from common clock binding.
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H A Dti,autoidle.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,autoidle.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI autoidle clock
10 - Tero Kristo <kristo@kernel.org>
11 - Sukrut Bellary <sbellary@baylibre.com>
14 Some clocks in TI SoC support the autoidle feature. These properties are
15 applicable only if the clock supports autoidle feature. It assumes a register
17 usage and configuration bit setting. Autoidle clock is never an individual
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H A Ddivider.txt4 register-mapped adjustable clock rate divider that does not gate and has
15 ti,index-starts-at-one - valid divisor values start at 1, not the default
22 ti,index-power-of-two - valid divisor values are powers of two. E.g:
39 Any zero value in this array means the corresponding bit-value is invalid
44 the number of bits to shift that mask, if necessary. If the shift value
45 is missing it is the same as supplying a zero shift.
47 This binding can also optionally provide support to the hardware autoidle
50 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
51 [2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
54 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
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H A Dapll.txt4 register-mapped APLL with usually two selectable input clocks
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
16 - #clock-cells : from common clock binding; shall be set to 0.
17 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
18 - reg : address and length of the register set for controlling the APLL.
20 "control" - contains the control register offset
21 "idlest" - contains the idlest register offset
22 "autoidle" - contains the autoidle register offset (OMAP2 only)
23 - ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
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H A Dti,fixed-factor-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
11 - Sukrut Bellary <sbellary@baylibre.com>
15 clock. This also uses the autoidle support from TI autoidle clock.
18 - $ref: ti,autoidle.yaml#
22 const: ti,fixed-factor-clock
24 "#clock-cells":
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H A Dti,divider-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock It assumes a register-mapped adjustable clock rate divider
25 ti,index-starts-at-one - valid divisor values start at 1, not the default
32 ti,index-power-of-two - valid divisor values are powers of two. E.g:
49 Any zero value in this array means the corresponding bit-value is invalid
54 the number of bits to shift that mask, if necessary. If the shift value
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H A Dinterface.txt4 quite much similar to the basic gate-clock [2], however,
7 clock) and hardware autoidle enable / disable.
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
13 - compatible : shall be one of:
14 "ti,omap3-interface-clock" - basic OMAP3 interface clock
15 "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
17 "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
19 "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
20 "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
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H A Dti,interface-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,interface-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock is quite much similar to the basic gate-clock[1], however,
16 clock) and hardware autoidle enable / disable.
18 [1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
23 - ti,omap3-interface-clock # basic OMAP3 interface clock
24 - ti,omap3-no-wait-interface-clock # interface clock which has no hardware
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
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H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
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H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
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H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
31 #clock-cells = <0>;
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/freebsd/sys/arm/ti/clk/
H A Dti_divider_clock.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
74 { "ti,divider-clock", TI_DIVIDER_CLOCK },
75 { "ti,composite-divider-clock", TI_COMPOSITE_DIVIDER_CLOCK },
83 sc->clkdom = clkdom_create(sc->sc_dev); in register_clk()
84 if (sc->clkdom == NULL) { in register_clk()
85 DPRINTF(sc->sc_dev, "Failed to create clkdom\n"); in register_clk()
89 err = clknode_div_register(sc->clkdom, &sc->div_def); in register_clk()
91 DPRINTF(sc->sc_dev, "clknode_div_register failed %x\n", err); in register_clk()
95 err = clkdom_finit(sc->clkdom); in register_clk()
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H A Dti_dpll_clock.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
92 { "ti,omap3-dpll-clock", TI_OMAP3_DPLL_CLOCK },
93 { "ti,omap3-dpll-core-clock", TI_OMAP3_DPLL_CORE_CLOCK },
94 { "ti,omap3-dpll-per-clock", TI_OMAP3_DPLL_PER_CLOCK },
95 { "ti,omap3-dpll-per-j-type-clock",TI_OMAP3_DPLL_PER_J_TYPE_CLOCK },
96 { "ti,omap4-dpll-clock", TI_OMAP4_DPLL_CLOCK },
97 { "ti,omap4-dpll-x2-clock", TI_OMAP4_DPLL_X2_CLOCK },
98 { "ti,omap4-dpll-core-clock", TI_OMAP4_DPLL_CORE_CLOCK },
99 { "ti,omap4-dpll-m4xen-clock", TI_OMAP4_DPLL_M4XEN_CLOCK },
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