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Searched +full:ast2600 +full:- +full:lpc +full:- +full:v2 (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/mfd/
H A Daspeed-lpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Aspeed Low Pin Count (LPC) Bus Controller
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
17 primary use case of the Aspeed LPC controller is as a slave on the bus
21 The LPC controller is represented as a multi-function device to account for the
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/linux/Documentation/devicetree/bindings/ipmi/
H A Daspeed,ast2400-kcs-bmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
13 The Aspeed BMC SoCs typically use the Keyboard-Controller-Style (KCS)
14 interfaces on the LPC bus for in-band IPMI communication with their host.
19 - description: Channel ID derived from reg
22 - aspeed,ast2400-kcs-bmc-v2
23 - aspeed,ast2500-kcs-bmc-v2
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/linux/Documentation/devicetree/bindings/soc/aspeed/
H A Duart-routing.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 ---
6 $id: http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Oskar Senft <osk@google.com>
13 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
17 the built-in UARTS and physical serial I/O ports.
20 This can be used to enable Host <-> BMC communication via UARTs, e.g. to
30 - enum:
31 - aspeed,ast2400-uart-routing
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/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-g6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
6 #include <dt-bindings/clock/ast2600-clock.h>
10 compatible = "aspeed,ast2600";
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
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/linux/drivers/char/ipmi/
H A Dkcs_bmc_aspeed.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2018, Intel Corporation.
6 #define pr_fmt(fmt) "aspeed-kcs-bmc: " fmt
27 #define DEVICE_NAME "ast-kcs-bmc"
34 * LPCyE Enable LPC channel y
35 * IBFIEy Input Buffer Full IRQ Enable for LPC channel y
36 * IRQxEy Assert SerIRQ x for LPC channel y (Deprecated, use IDyIRQX, IRQXEy)
37 * IDyIRQX Use the specified 4-bit SerIRQ for LPC channel y
38 * SELyIRQX SerIRQ polarity for LPC channel y (low: 0, high: 1)
39 * IRQXEy Assert the SerIRQ specified in IDyIRQX for LPC channel y
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/linux/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed-g5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/pinctrl/pinconf-generic.h>
21 #include "../pinctrl-utils.h"
22 #include "pinctrl-aspeed.h"
32 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
35 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
45 #define SCU80 0x80 /* Multi-function Pin Control #1 */
46 #define SCU84 0x84 /* Multi-function Pin Control #2 */
47 #define SCU88 0x88 /* Multi-function Pin Control #3 */
48 #define SCU8C 0x8C /* Multi-function Pin Control #4 */
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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