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/linux/Documentation/devicetree/bindings/gpio/
H A Daspeed,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
13 This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
15 AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
16 GPIO pins can be programmed to support the following options
17 - Support interrupt option for each input port and various interrupt
18 sensitivity option (level-high, level-low, edge-high, edge-low)
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/linux/drivers/fsi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 FSI - the FRU Support Interface - is a simple bus for low-level
12 access to POWER-based hardware.
29 symlinks in /dev/fsi/by-path when this option is enabled.
32 tristate "GPIO-based FSI master"
36 This option enables a FSI master driver using GPIO lines.
52 This option enables a FSI master using the AST2400 and AST2500 GPIO
84 a pipe-like FSI device for communicating with the self boot engine
91 This option enables an SBEFIFO based On-Chip Controller (OCC) device
H A Dcf-fsi-fw.h1 /* SPDX-License-Identifier: GPL-2.0+ */
43 #define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */
45 #define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */
46 #define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */
47 #define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */
48 #define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */
49 #define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */
50 #define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */
61 * +---------------------------+
64 * +---------------------------+
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H A Dfsi-master-ast-cf.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/gpio/consumer.h>
21 #include <linux/gpio/aspeed.h>
25 #include "fsi-master.h"
26 #include "cf-fsi-fw.h"
28 #define FW_FILE_NAME "cf-fsi-fw.bin"
132 msg->msg <<= bits; in msg_push_bits()
133 msg->msg |= data & ((1ull << bits) - 1); in msg_push_bits()
134 msg->bits += bits; in msg_push_bits()
142 top = msg->bits & 0x3; in msg_push_crc()
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/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-microsoft-olympus.dts1 //SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "aspeed-g4.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
10 compatible = "microsoft,olympus-bmc", "aspeed,ast2400";
13 stdout-path = &uart5;
21 reserved-memory {
22 #address-cells = <1>;
23 #size-cells = <1>;
27 no-map;
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H A Daspeed-bmc-opp-vesnin.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "aspeed-g4.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
10 compatible = "yadro,vesnin-bmc", "aspeed,ast2400";
13 stdout-path = &uart5;
21 reserved-memory {
22 #address-cells = <1>;
23 #size-cells = <1>;
27 no-map;
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H A Daspeed-bmc-delta-ahe50dc.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g4.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
9 compatible = "regulator-output"; \
10 vout-supply = <&efuse##n>; \
19 shunt-resistor-micro-ohms = <675>; \
22 regulator-name = __stringify(efuse##num##-reg); \
28 model = "Delta Power AHE-50DC";
29 compatible = "delta,ahe50dc-bmc", "aspeed,ast2400";
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H A Daspeed-bmc-quanta-q71l.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3 #include "aspeed-g4.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
8 compatible = "quanta,q71l-bmc", "aspeed,ast2400";
30 stdout-path = &uart5;
38 reserved-memory {
39 #address-cells = <1>;
40 #size-cells = <1>;
44 no-map;
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/linux/Documentation/devicetree/bindings/serial/
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
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/linux/drivers/irqchip/
H A Dirq-aspeed-vic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
7 * Based on irq-vic.c:
9 * Copyright (C) 1999 - 2003 ARM Limited
63 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); in vic_init_hw()
64 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); in vic_init_hw()
67 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); in vic_init_hw()
68 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); in vic_init_hw()
71 writel(0, vic->base + AVIC_INT_SELECT); in vic_init_hw()
72 writel(0, vic->base + AVIC_INT_SELECT + 4); in vic_init_hw()
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/linux/drivers/gpio/
H A Dgpio-aspeed-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/gpio/driver.h>
50 * Note: The "value" register returns the input value when the GPIO is
53 * The "rdata" register returns the output value when the GPIO is
105 static void __iomem *bank_reg(struct aspeed_sgpio *gpio, in bank_reg() argument
111 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
113 return gpio->base + bank->rdata_reg; in bank_reg()
115 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
117 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
119 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
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H A Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/gpio/aspeed.h>
11 #include <linux/gpio/driver.h>
26 * These two headers aren't meant to be used by GPIO drivers. We need
31 #include <linux/gpio/consumer.h>
34 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
35 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
36 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
76 * represents disabled debouncing for the GPIO. Any other value for an element
110 * line even when the GPIO is configured as an output. Since
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # GPIO infrastructure and drivers
10 bool "GPIO Support"
12 This enables GPIO support through the generic GPIO library.
14 one or more of the GPIO drivers below.
50 this symbol, but new drivers should use the generic gpio-regmap
54 bool "Debug GPIO calls"
57 Say Y here to add some extra checks and diagnostics to GPIO calls.
60 non-sleeping contexts. They can make bitbanged serial protocols
65 bool "/sys/class/gpio/... (sysfs interface)" if EXPERT
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/linux/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include "pinctrl-aspeed.h"
18 return pdata->pinmux.ngroups; in aspeed_pinctrl_get_groups_count()
26 return pdata->pinmux.groups[group].name; in aspeed_pinctrl_get_group_name()
35 *pins = &pdata->pinmux.groups[group].pins[0]; in aspeed_pinctrl_get_group_pins()
36 *npins = pdata->pinmux.groups[group].npins; in aspeed_pinctrl_get_group_pins()
44 seq_printf(s, " %s", dev_name(pctldev->dev)); in aspeed_pinctrl_pin_dbg_show()
51 return pdata->pinmux.nfunctions; in aspeed_pinmux_get_fn_count()
59 return pdata->pinmux.functions[function].name; in aspeed_pinmux_get_fn_name()
69 *groups = pdata->pinmux.functions[function].groups; in aspeed_pinmux_get_fn_groups()
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H A Dpinmux-aspeed.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * The ASPEED SoCs provide typically more than 200 pins for GPIO and other
21 * read-only).
23 * SoC Multi-function Pin Expression Examples
24 * ------------------------------------------
26 * Here are some sample mux configurations from the AST2400 and AST2500
30 * D6 is a pin with a single function (beside GPIO); a high priority signal
34 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
36 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
38 * C5 is a multi-signal pin (high and low priority signals). Here we touch
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H A Dpinctrl-aspeed-g4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/pinctrl/pinconf-generic.h>
20 #include "../pinctrl-utils.h"
21 #include "pinmux-aspeed.h"
22 #include "pinctrl-aspeed.h"
32 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
35 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
42 #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
44 #define SCU80 0x80 /* Multi-function Pin Control #1 */
45 #define SCU84 0x84 /* Multi-function Pin Control #2 */
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H A Dpinctrl-aspeed-g5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/pinctrl/pinconf-generic.h>
21 #include "../pinctrl-utils.h"
22 #include "pinctrl-aspeed.h"
32 * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
35 * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
43 #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
45 #define SCU80 0x80 /* Multi-function Pin Control #1 */
46 #define SCU84 0x84 /* Multi-function Pin Control #2 */
47 #define SCU88 0x88 /* Multi-function Pin Control #3 */
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/linux/drivers/hwmon/
H A Daspeed-pwm-tacho.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/gpio/consumer.h>
11 #include <linux/hwmon-sysfs.h>
47 /* ASPEED_PTCR_CTRL : 0x00 - General Control Register */
74 /* ASPEED_PTCR_CLK_CTRL : 0x04 - Clock Control Register */
87 * ASPEED_PTCR_DUTY_CTRL/1/2/3 : 0x08/0x0C/0x48/0x4C - PWM-FAN duty control
97 /* ASPEED_PTCR_TYPEM_CTRL : 0x10/0x18/0x50 - Type M/N/O Ctrl 0 Register */
105 /* ASPEED_PTCR_TACH_SOURCE : 0x20/0x60 - Tach Source Register */
112 /* ASPEED_PTCR_RESULT : 0x2c - Result Register */
116 /* ASPEED_PTCR_CTRL_EXT : 0x40 - General Control Extension #1 Register */
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