/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mp-nominal.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 13 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 19 assigned-clock-rates = <0>, <0>, 24 fsl,operating-mode = "nominal"; 28 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 29 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 30 assigned-clock-rates = <800000000>; 34 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 36 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, [all …]
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H A D | imx8mm-overdrive.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, 6 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 7 assigned-clock-rates = <0>, <1000000000>; 11 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, 13 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 14 assigned-clock-rates = <0>, <1000000000>; 18 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, 22 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, 25 assigned-clock-rates = <750000000>,
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H A D | imx8ulp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/imx8ulp-clock.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/power/imx8ulp-power.h> 10 #include <dt-bindings/thermal/thermal.h> 12 #include "imx8ulp-pinfunc.h" 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; [all …]
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H A D | imx8mm-beacon-baseboard.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 #include <dt-bindings/phy/phy-imx8-pcie.h> 10 dmic_codec: dmic-codec { 11 compatible = "dmic-codec"; 12 num-channels = <1>; 13 #sound-dai-cells = <0>; 17 compatible = "gpio-leds"; 22 default-state = "off"; 28 default-state = "off"; 34 default-state = "off"; [all …]
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H A D | imx8mm-emcon.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 /dts-v1/; 13 stdout-path = &uart1; 17 compatible = "gpio-leds"; 18 pinctrl-names = "default"; 19 pinctrl-0 = <&pinctrl_gpio_led>; 21 led-green { 24 default-state = "on"; 25 linux,default-trigger = "heartbeat"; 28 led-red { [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 4 --- 5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Kishon Vijay Abraham I <kishon@ti.com> 16 - ti,j721e-wiz-16g 17 - ti,j721e-wiz-10g 18 - ti,j721s2-wiz-10g 19 - ti,am64-wiz-10g [all …]
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H A D | mixel,mipi-dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Guido Günther <agx@sigxcpu.org> 13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the 14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the 18 in either MIPI-DSI PHY mode or LVDS PHY mode. 23 - fsl,imx8mq-mipi-dphy 24 - fsl,imx8qxp-mipi-dphy [all …]
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/linux/drivers/clk/ |
H A D | clk-conf.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <linux/clk-provider.h> 9 #include <linux/clk/clk-conf.h> 21 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents() 22 "#clock-cells"); in __set_clk_parents() 23 if (num_parents == -EINVAL) in __set_clk_parents() 24 pr_err("clk: invalid value of clock-parents property at %pOF\n", in __set_clk_parents() 28 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in __set_clk_parents() 29 "#clock-cells", index, &clkspec); in __set_clk_parents() 32 if (rc == -ENOENT) in __set_clk_parents() [all …]
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx7ulp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright 2017-2018 NXP 8 #include <dt-bindings/clock/imx7ulp-clock.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include "imx7ulp-pinfunc.h" 15 interrupt-parent = <&intc>; 17 #address-cells = <1>; 18 #size-cells = <1>; 37 #address-cells = <1>; [all …]
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H A D | imx7d-pico.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 /dts-v1/; 11 compatible = "pwm-backlight"; 13 brightness-levels = <0 36 72 108 144 180 216 255>; 14 default-brightness-level = <6>; 24 compatible = "vxt,vl050-8048nt-c01"; 26 power-supply = <®_lcd_3v3>; 30 remote-endpoint = <&display_out>; 35 reg_lcd_3v3: regulator-lcd-3v3 { 36 compatible = "regulator-fixed"; [all …]
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H A D | imx7d-zii-rpu2.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 5 * RPU - Remote Peripheral Unit 10 /dts-v1/; 11 #include <dt-bindings/thermal/thermal.h> 16 compatible = "zii,imx7d-rpu2", "fsl,imx7d"; 19 stdout-path = &uart2; 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <24576000>; 28 cs2000_in_dummy: dummy-oscillator { [all …]
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/linux/Documentation/devicetree/bindings/sound/ |
H A D | nvidia,tegra-audio-graph-card.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 12 additional standard clock DT bindings required for Tegra. 15 - Jon Hunter <jonathanh@nvidia.com> 16 - Sameer Pujar <spujar@nvidia.com> 19 - $ref: audio-graph.yaml# 24 - nvidia,tegra210-audio-graph-card 25 - nvidia,tegra186-audio-graph-card [all …]
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H A D | nvidia,tegra210-ahub.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 for audio pre-processing, post-processing and a programmable full 17 - Jon Hunter <jonathanh@nvidia.com> 18 - Sameer Pujar <spujar@nvidia.com> 22 pattern: "^ahub@[0-9a-f]*$" 26 - enum: 27 - nvidia,tegra210-ahub [all …]
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H A D | nvidia,tegra186-dspk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 Density Modulation (PDM) transmitter that up-samples the input to 13 over sampled Pulse Code Modulation (PCM) input to the desired 1-bit 17 - Jon Hunter <jonathanh@nvidia.com> 18 - Sameer Pujar <spujar@nvidia.com> 21 - $ref: dai-common.yaml# 25 pattern: "^dspk@[0-9a-f]*$" [all …]
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H A D | nvidia,tegra210-dmic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-dmic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 16 - Jon Hunter <jonathanh@nvidia.com> 17 - Sameer Pujar <spujar@nvidia.com> 20 - $ref: dai-common.yaml# 24 pattern: "^dmic@[0-9a-f]*$" 28 - const: nvidia,tegra210-dmic 29 - items: [all …]
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H A D | nvidia,tegra210-i2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 The Inter-IC Sound (I2S) controller implements full-duplex, 11 bi-directional and single direction point-to-point serial 16 - Jon Hunter <jonathanh@nvidia.com> 17 - Sameer Pujar <spujar@nvidia.com> 20 - $ref: dai-common.yaml# 24 pattern: "^i2s@[0-9a-f]*$" [all …]
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H A D | brcm,cygnus-audio.txt | 4 - compatible : "brcm,cygnus-audio" 5 - #address-cells: 32bit valued, 1 cell. 6 - #size-cells: 32bit valued, 0 cell. 7 - reg : Should contain audio registers location and length 8 - reg-names: names of the registers listed in "reg" property 12 - clocks: PLL and leaf clocks used by audio ports 13 - assigned-clocks: PLL and leaf clocks 14 - assigned-clock-parents: parent clocks of the assigned clocks 16 - assigned-clock-rates: List of clock frequencies of the 17 assigned clocks [all …]
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/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos4412-odroid-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards 7 #include <dt-bindings/sound/samsung-i2s.h> 8 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/clock/maxim,max77686.h> 11 #include "exynos4412-ppmu-common.dtsi" 12 #include <dt-bindings/gpio/gpio.h> 13 #include "exynos-mfc-reserved-memory.dtsi" 22 stdout-path = &serial_1; 26 compatible = "samsung,secure-firmware"; [all …]
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H A D | exynos4412-itop-elite.dts | 1 // SPDX-License-Identifier: GPL-2.0 13 /dts-v1/; 14 #include <dt-bindings/leds/common.h> 15 #include <dt-bindings/pwm/pwm.h> 16 #include <dt-bindings/sound/samsung-i2s.h> 17 #include "exynos4412-itop-scp-core.dtsi" 21 compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4"; 29 stdout-path = "serial2:115200n8"; 33 compatible = "gpio-leds"; 39 default-state = "off"; [all …]
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/linux/arch/arm64/boot/dts/ti/ |
H A D | k3-am65-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 7 #include <dt-bindings/phy/phy-am654-serdes.h> 11 compatible = "mmio-sram"; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 atf-sram@0 { 21 sysfw-sram@f0000 { 25 l3cache-sram@100000 { 30 gic500: interrupt-controller@1800000 { [all …]
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H A D | k3-j721e-common-proc-board.dts | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 3 * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/ 8 /dts-v1/; 10 #include "k3-j721e-som-p0.dtsi" 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/net/ti-dp83867.h> 14 #include <dt-bindings/phy/phy-cadence.h> 17 compatible = "ti,j721e-evm", "ti,j721e"; 33 stdout-path = "serial2:115200n8"; [all …]
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/linux/Documentation/devicetree/bindings/ufs/ |
H A D | ti,j721e-ufs.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Vignesh Raghavendra <vigneshr@ti.com> 15 - const: ti,j721e-ufs 23 description: phandle to the M-PHY clock 25 power-domains: 28 assigned-clocks: 31 assigned-clock-parents: [all …]
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/linux/Documentation/devicetree/bindings/rtc/ |
H A D | st,stm32-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics STM32 Real Time Clock 10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com> 15 - st,stm32-rtc 16 - st,stm32h7-rtc 17 - st,stm32mp1-rtc 18 - st,stm32mp25-rtc [all …]
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/linux/arch/arm/boot/dts/mediatek/ |
H A D | mt7629.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/clock/mt7629-clk.h> 11 #include <dt-bindings/power/mt7622-power.h> 12 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/phy/phy.h> 14 #include <dt-bindings/reset/mt7629-resets.h> 18 interrupt-parent = <&sysirq>; 19 #address-cells = <1>; [all …]
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/linux/Documentation/devicetree/bindings/arm/ |
H A D | sp810.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andre Przywara <andre.przywara@arm.com> 22 - compatible 27 - const: arm,sp810 28 - const: arm,primecell 33 clock-names: 35 - const: refclk 36 - const: timclk [all …]
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