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Searched +full:assert +full:- +full:falling +full:- +full:edge (Results 1 – 20 of 20) sorted by relevance

/linux/sound/drivers/
H A Dportman2x4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) by Levent Guendogdu <levon@feature-it.com>
9 * - cleanup and rewrite
11 * - source code cleanup
13 * - fixed compilation problem with alsa 1.0.6a (removed MODULE_CLASSES,
17 * - adde
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/linux/Documentation/devicetree/bindings/gpio/
H A Drealtek,rtd-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpio/realtek,rtd-gpio.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Tzuyi Chang <tychang@realtek.com>
15 RTD series SoC family, which are high-definition media processor SoCs.
20 - realtek,rtd1295-misc-gpio
21 - realtek,rtd1295-iso-gpio
22 - realtek,rtd1315e-iso-gpio
23 - realtek,rtd1319-iso-gpio
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-odyssey.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp157c-odyssey-som.dtsi"
11 model = "Seeed Studio Odyssey-STM32MP157C Board";
12 compatible = "seeed,stm32mp157c-odyssey",
13 "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
21 stdout-path = "serial0:115200n8";
26 pinctrl-names = "default", "sleep";
27 pinctrl-0 = <&dcmi_pins_b>;
28 pinctrl-1 = <&dcmi_sleep_pins_b>;
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/linux/drivers/pinctrl/qcom/
H A Dtlmm-test.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #define pr_fmt(fmt) "tlmm-test: " fmt
23 * (pinctrl-msm) delivers expected number of interrupts in response to changing
27 * "gpio", which the tester is expected to specify an unused and non-connected
41 static int tlmm_test_gpio = -1;
57 * struct tlmm_test_priv - Per-test context
102 if (priv->intr_op & TLMM_TEST_COUNT) in tlmm_test_intr_fn()
103 atomic_inc(&priv->intr_count); in tlmm_test_intr_fn()
105 if (priv->intr_op & TLMM_TEST_OUTPUT_LOW) in tlmm_test_intr_fn()
107 if (priv->intr_op & TLMM_TEST_OUTPUT_HIGH) in tlmm_test_intr_fn()
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/linux/drivers/scsi/
H A DNCR5380.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * +1 (303) 666-5836
19 * 1+ (719) 578-3400
20 * 1+ (800) 334-5454
65 * either arbitration is occurring or the phase-indicating signals (
66 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
74 #define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
76 #define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
79 #define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
80 #define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
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/linux/drivers/pps/clients/
H A Dpps-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pps-gpio.c -- PPS client driver using GPIO
9 #define PPS_GPIO_NAME "pps-gpio"
55 /* Small trick to bypass the check on edge's direction when capture_clear is unset */ in pps_gpio_irq_handler()
56 rising_edge = info->capture_clear ? in pps_gpio_irq_handler()
57 gpiod_get_value(info->gpio_pin) : !info->assert_falling_edge; in pps_gpio_irq_handler()
58 if ((rising_edge && !info->assert_falling_edge) || in pps_gpio_irq_handler()
59 (!rising_edge && info->assert_falling_edge)) in pps_gpio_irq_handler()
60 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
61 else if (info->capture_clear && in pps_gpio_irq_handler()
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/linux/drivers/usb/dwc3/
H A Ddwc3-qcom-legacy.c1 // SPDX-License-Identifier: GPL-2.0
4 * Inspired by dwc3-of-simple.c
122 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
124 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
127 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
129 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
141 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST; in dwc3_qcom_vbus_notifier()
153 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL; in dwc3_qcom_host_notifier()
160 struct device *dev = qcom->dev; in dwc3_qcom_register_extcon()
164 if (!of_property_present(dev->of_node, "extcon")) in dwc3_qcom_register_extcon()
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/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
26 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
29 #include "../pinctrl-utils.h"
33 #define DRIVER_NAME "pinctrl-starfive"
37 * https://github.com/starfive-tech/JH7100_Docs
48 * The following 32-bit registers come in pairs, but only the offset of the
49 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
50 * the second GPIO 32-63.
54 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
55 * interrupt is level-triggered.
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H A Dpinctrl-starfive-jh7110.c1 // SPDX-License-Identifier: GPL-2.0
27 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
30 #include "../pinctrl-utils.h"
33 #include "pinctrl-starfive-jh7110.h"
52 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
100 const struct jh7110_pinctrl_soc_info *info = sfp->info; in jh7110_pin_dbg_show()
102 seq_printf(s, "%s", dev_name(pctldev->dev)); in jh7110_pin_dbg_show()
104 if (pin < sfp->gc.ngpio) { in jh7110_pin_dbg_show()
107 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset); in jh7110_pin_dbg_show()
108 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset); in jh7110_pin_dbg_show()
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/linux/drivers/ata/
H A Dpata_octeon_cf.c8 * Copyright (C) 2005 - 2012 Cavium Inc.
31 * -- 8 bits no irq, no DMA
32 * -- 16 bits no irq, no DMA
33 * -- 16 bits True IDE mode with DMA, but no irq.
106 reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */ in octeon_cf_set_boot_reg_cfg()
108 reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */ in octeon_cf_set_boot_reg_cfg()
128 struct octeon_cf_port *cf_port = ap->private_data; in octeon_cf_set_piomode()
150 BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T)); in octeon_cf_set_piomode()
154 t2--; in octeon_cf_set_piomode()
158 trh--; in octeon_cf_set_piomode()
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/linux/lib/zstd/decompress/
H A Dzstd_decompress_block.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
15 /*-*******************************************************
51 /*-*************************************************************
57 …size_t const blockSizeMax = dctx->isFrameDecompression ? dctx->fParams.blockSizeMax : ZSTD_BLOCKSI… in ZSTD_blockSizeMax()
58 assert(blockSizeMax <= ZSTD_BLOCKSIZE_MAX); in ZSTD_blockSizeMax()
71 bpPtr->lastBlock = cBlockHeader & 1; in ZSTD_getcBlockSize()
72 bpPtr->blockType = (blockType_e)((cBlockHeader >> 1) & 3); in ZSTD_getcBlockSize()
73 bpPtr->origSize = cSize; /* only useful for RLE */ in ZSTD_getcBlockSize()
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-usb2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
11 #include <linux/extcon-provider.h>
50 * enum usb_chg_state - Different states involved in USB charger detection.
89 * struct rockchip_chg_det_reg - usb charger detect registers
92 * @dp_det: assert data pin connect successfully.
115 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
120 * @disfall_en: host disconnect fall edge detection enable.
121 * @disfall_st: host disconnect fall edge detection state.
122 * @disfall_clr: host disconnect fall edge detection clear.
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
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/linux/lib/zstd/compress/
H A Dzstd_compress.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
12 /*-*************************************
46 * Maximum size of the hash table dedicated to find 3-bytes matches,
57 /*-*************************************
62 * the one-pass compression functions.
75 /*-*************************************
90 … * row-based matchfinder. Unless the cdict is reloaded, we will use
102 assert(cctx != NULL); in ZSTD_initCCtx()
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/linux/drivers/tty/serial/
H A Dsc16is7xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - common code
53 * - only on 75x/76x
56 * - only on 75x/76x
59 * - only on 75x/76x
62 * - only on 75x/76x
90 /* IER register bits - write only if (EFR[4] == 1) */
103 /* FCR register bits - write only if (EFR[4] == 1) */
113 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
115 * - only on 75x/76x
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/linux/drivers/comedi/drivers/
H A Dni_mio_common.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Hardware driver for DAQ-STC based boards
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
17 * 340747b.pdf AT-MIO E series Register Level Programmer Manual
19 * 340934b.pdf DAQ-STC reference manual
31 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
32 * 321808a.pdf about at-mio-16e-10 rev P
33 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
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/linux/drivers/net/ethernet/sun/
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
104 len of non-reassembly pkt
183 #define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
185 #define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
216 reset when hot-swap is being
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/linux/drivers/mtd/nand/raw/
H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
47 * --------------------------------------------+
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/linux/kernel/bpf/
H A Dverifier.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
7 #include <linux/bpf-cgroup.h>
23 #include <linux/error-injection.h>
60 * The first pass is depth-first-search to check that the program is a DAG.
62 * - larger than BPF_MAXINSNS insns
63 * - if loop is present (detected via back-edge)
64 * - unreachable insns exist (shouldn't be a forest. program = one function)
65 * - out of bounds or malformed jumps
77 * All registers are 64-bit.
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nocmcff -- Disable firmware first mode for corrected
28 nospcr -- disable console in ACPI SPCR table as
45 If set to vendor, prefer vendor-specific driver
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