| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,coresight-cti.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-ct
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| H A D | coresight-cti.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 number is defined at design time, the maximum of each defined in the DEVID
26 programmable channels, usually 4, but again implementation defined and
32 are implementation defined, except when the CTI is connected to an ARM v8
37 architecturally connected CTI an additional compatible string is used to
38 indicate this feature (arm,coresight-cti-v8-arch).
52 and usages. These can be defined along with the signal indexes with the
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
20 interrupt map is defined by the ISA it's not listed in the HLIC's device tree
27 - compatible : "riscv,cpu-intc"
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| H A D | riscv,cpu-intc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
22 the HLIC, which are routed via the platform-level interrupt controller
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| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | arm,arch_timer_mmio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
37 clock-frequency:
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| H A D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - const: arm,cortex-a15-timer
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Pipeline.h | 1 //===--------------------- Pipeline.h ---------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
28 /// It emulates an out-of-order execution of instructions. Instructions are
35 /// executing and register writes are architecturally committed.
40 /// is defined by the SourceMgr object, which is managed by the initial stage
|
| /freebsd/lib/libpmc/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 108 …architecturally defined event. This event counts the number of retired branch instructions that we…
117 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
127 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
137 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
147 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
157 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
165 …by dividing the event count by the core frequency. This event is architecturally defined and is a …
190 …lapsed time while the core was not in halt state. This event is architecturally defined and is a …
207 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last …
216 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/ |
| H A D | RetireControlUnit.h | 1 //===---------------------- RetireControlUnit.h -----------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
25 /// This class tracks which instructions are in-flight (i.e., dispatched but not
33 /// On instruction retired, register updates are all architecturally
42 // flag set, then the instruction has reached the write-back stage and will
49 // Note that the size of the reorder buffer is defined by the scheduling
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| /freebsd/contrib/llvm-project/compiler-rt/lib/scudo/standalone/include/scudo/ |
| H A D | interface.h | 1 //===-- scudo/interface.h --------
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| /freebsd/sys/riscv/include/ |
| H A D | vmm.h | 2 * SPDX-License-Identifier: BSD-2-Clause
56 * Identifiers for architecturally defined registers.
173 return (*((uintptr_t *)(info->rptr)) != 0); in vcpu_rendezvous_pending()
180 return (*info->sptr); in vcpu_suspended()
208 return (td->td_ast != 0 || td->td_owepreempt != 0); in vcpu_should_yield()
|
| /freebsd/sys/amd64/include/ |
| H A D | vmm.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
53 * Identifiers for architecturally defined registers.
144 (SPECNAMELEN - VM_MAX_PREFIXLEN - VM_MAX_SUFFIXLEN - 1)
202 vmi_init_func_t init; /* vm-specific initialization */
319 return (CPU_ISSET(vcpu_vcpuid(vcpu), info->rptr)); in vcpu_rendezvous_pending()
326 return (*info->sptr); in vcpu_suspended()
333 return (*info->iptr); in vcpu_reqidle()
371 return (td->td_ast != 0 || td->td_owepreempt != 0); in vcpu_should_yield()
386 * success and non-zero on failure.
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| /freebsd/sys/arm64/include/ |
| H A D | vmm.h | 49 * Identifiers for architecturally defined registers.
126 (SPECNAMELEN - VM_MAX_PREFIXLEN - VM_MAX_SUFFIXLEN - 1)
192 return (*((uintptr_t *)(info->rptr)) != 0); in vcpu_rendezvous_pending()
199 return (*info->sptr); in vcpu_suspended()
227 return (td->td_ast != 0 || td->td_owepreempt != 0); in vcpu_should_yield()
|
| /freebsd/sys/arm/arm/ |
| H A D | swtch-v6.S | 3 /*-
37 /*-
38 * Copyright (c) 1994-1998 Mark Brinicombe.
89 #if defined(SMP)
140 * is not architecturally invisible. See ARM Architecture Reference
141 * Manual ARMv7-A and ARMv7-R edition, page B2-1264(65), Branch
148 * is effectively NOP on Cortex-A15 so it needs special treatment.
154 /* Branch Target Cache on Cortex-A15. */
238 ldr r6, [r11, #(TD_PROC)] /* newtd->proc */
239 ldr r6, [r6, #(P_VMSPACE)] /* newtd->proc->vmspace */
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| /freebsd/usr.bin/clang/llvm-mca/ |
| H A D | llvm-mca.1 | 4 .nr rst2man-indent-level 0
7 \\$1 \\n[an-margin]
8 level \\n[rst2man-indent-level]
9 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
10 -
11 \\n[rst2man-indent0]
12 \\n[rst2man-indent1]
13 \\n[rst2man-indent2]
18 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin]
19 . nr rst2man-indent-level +1
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| /freebsd/lib/libpmc/ |
| H A D | pmc.westmere.3 | 44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
69 .Bl -column "PMC_CAP_INTERRUPT" "Support"
86 .Bl -tag -width indent
88 Configure the Off-core Response bits.
89 .Bl -tag -width indent
114 I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences,
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| H A D | pmc.corei7.3 | 44 .Bl -tag -width "Li PMC_CLASS_IAP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the Off-core Response bits.
90 .Bl -tag -width indent
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| /freebsd/sys/i386/include/ |
| H A D | atomic.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 * The open-coded number is used instead of the symbolic expression to
71 * atomic_subtract_char(P, V) (*(u_char *)(P) -= (V))
76 * atomic_subtract_short(P, V) (*(u_short *)(P) -= (V))
81 * atomic_subtract_int(P, V) (*(u_int *)(P) -= (V))
88 * atomic_subtract_long(P, V) (*(u_long *)(P) -= (V))
135 * Returns 0 on failure, non-zero on success.
233 * Guide, and not mfence. In the kernel, we use a private per-cpu
244 #if defined(_KERNEL)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // the AArch64 target useful for the compiler back-end and the MC libraries.
14 //===----------------------------------------------------------------------===//
253 // The CondCodes constants map directly to the 4-bit encoding of the condition
255 enum CondCode { // Meaning (integer) Meaning (floating-point)
533 /// An enum to describe what types of loops we should attempt to tail-fold:
536 /// Recurrences: Loops with first-order recurrences, i.e. that would
540 /// or first-order recurrences.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SpeculationHardening.cpp | 1 //===- AArch64SpeculationHardening.cpp - Harden Against Missspeculation --===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===--
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
63 CPU = "apple-a12"; in createAArch64MCSubtargetInfo()
303 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); in initLLVMToCVRegMapping()
363 MAI->addInitialFrameState(Inst); in createAArch64MCAsmInfo()
414 // Search for a PC-relative argument. in evaluateBranch()
417 const auto &Desc = Info->get(Inst.getOpcode()); in evaluateBranch()
424 Target = (Addr & -4096) + Imm * 4096; in evaluateBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
49 // SSE2 should default to enabled in 64-bit mode, but can be turned off in ParseX86Triple()
52 FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2"; in ParseX86Triple()
54 FS = "-64bit-mode,+32bit-mode,-16bit-mode"; in ParseX86Triple()
56 FS = "-64bit-mode,-32bit-mode,+16bit-mode"; in ParseX86Triple()
101 assert(Index.isReg() && Index.getReg() == 0 && "Invalid eip-based address"); in is32BitMemOperand()
171 unsigned SEH = MRI->getEncodingValue(Reg); in initLLVMToSEHAndCVRegMapping()
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| /freebsd/sys/x86/iommu/ |
| H A D | intel_drv.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
32 #if defined(__amd64__)
105 ptrend = (char *)dmartbl + dmartbl->Header.Length; in dmar_iterate_tbl()
110 if (dmarh->Length <= 0) { in dmar_iterate_tbl()
112 dmarh->Length); in dmar_iterate_tbl()
115 ptr += dmarh->Length; in dmar_iterate_tbl()
132 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) in dmar_find_iter()
136 if (fia->i == 0) { in dmar_find_iter()
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| /freebsd/sys/arm64/vmm/io/ |
| H A D | vgic_v3.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (C) 2020-2022 Andrew Turner
79 #define VGIC_SGI_NUM (GIC_LAST_SGI - GIC_FIRST_SGI + 1)
80 #define VGIC_PPI_NUM (GIC_LAST_PPI - GIC_FIRST_PPI + 1)
81 #define VGIC_SPI_NUM (GIC_LAST_SPI - GIC_FIRST_SPI + 1)
127 /* Per-CPU data not needed by EL2 */
209 /* GICD_STATUSR - RAZ/WI as we don't report errors (yet) */
212 /* GICD_SETSPI_SR - RAZ/WI */
213 /* GICD_CLRSPI_SR - RAZ/WI */
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| /freebsd/sys/arm64/arm64/ |
| H A D | identcpu.c | 1 /*-
88 * The default implementation of I-cache sync assumes we have an
103 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) in sysctl_hw_machine()
120 architecturally. */
122 * Per-CPU affinity as provided in MPIDR_EL1
128 * Aff1 - Cluster number
129 * Aff0 - CPU number in Aff1 cluster
177 return (&cpu_desc[cpu - 1]); in get_cpu_desc()
190 * Part number is implementation defined
198 * Per-implementer table of (PartNum, CPU Name) pairs.
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