Lines Matching +full:architecturally +full:- +full:defined
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
32 #if defined(__amd64__)
105 ptrend = (char *)dmartbl + dmartbl->Header.Length; in dmar_iterate_tbl()
110 if (dmarh->Length <= 0) { in dmar_iterate_tbl()
112 dmarh->Length); in dmar_iterate_tbl()
115 ptr += dmarh->Length; in dmar_iterate_tbl()
132 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) in dmar_find_iter()
136 if (fia->i == 0) { in dmar_find_iter()
137 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; in dmar_find_iter()
140 fia->i--; in dmar_find_iter()
159 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) in dmar_count_iter()
176 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_AFFINITY) { in dmar_rhsa_iter()
179 if (adr->BaseAddress == ria->base) in dmar_rhsa_iter()
180 ria->proxim_dom = adr->ProximityDomain; in dmar_rhsa_iter()
207 haw = dmartbl->Width + 1; in dmar_identify()
213 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, in dmar_identify()
214 (unsigned)dmartbl->Flags, in dmar_identify()
236 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); in dmar_identify()
240 i, (uintmax_t)dmarh->Address, error); in dmar_identify()
246 ria.base = dmarh->Address; in dmar_identify()
247 ria.proxim_dom = -1; in dmar_identify()
249 acpi_set_domain(dmar_devs[i], ria.proxim_dom == -1 ? in dmar_identify()
270 iommu_fini_busdma(&unit->iommu); in dmar_release_resources()
276 if (unit->regs != NULL) { in dmar_release_resources()
277 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, in dmar_release_resources()
278 unit->regs); in dmar_release_resources()
279 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, in dmar_release_resources()
280 unit->regs); in dmar_release_resources()
281 unit->regs = NULL; in dmar_release_resources()
283 if (unit->domids != NULL) { in dmar_release_resources()
284 delete_unrhdr(unit->domids); in dmar_release_resources()
285 unit->domids = NULL; in dmar_release_resources()
287 if (unit->ctx_obj != NULL) { in dmar_release_resources()
288 vm_object_deallocate(unit->ctx_obj); in dmar_release_resources()
289 unit->ctx_obj = NULL; in dmar_release_resources()
291 sysctl_ctx_free(&unit->iommu.sysctl_ctx); in dmar_release_resources()
306 dmd = &unit->x86c.intrs[i]; in dmar_remap_intr()
307 if (irq == dmd->irq) { in dmar_remap_intr()
314 dmd->msi_data = msi_data; in dmar_remap_intr()
315 dmd->msi_addr = msi_addr; in dmar_remap_intr()
316 (dmd->disable_intr)(DMAR2IOMMU(unit)); in dmar_remap_intr()
317 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); in dmar_remap_intr()
318 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); in dmar_remap_intr()
319 dmar_write4(unit, dmd->msi_uaddr_reg, in dmar_remap_intr()
320 dmd->msi_addr >> 32); in dmar_remap_intr()
321 (dmd->enable_intr)(DMAR2IOMMU(unit)); in dmar_remap_intr()
337 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), in dmar_print_caps()
338 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, in dmar_print_caps()
339 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); in dmar_print_caps()
340 caphi = unit->hw_cap >> 32; in dmar_print_caps()
341 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, in dmar_print_caps()
345 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), in dmar_print_caps()
346 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), in dmar_print_caps()
347 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); in dmar_print_caps()
348 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) in dmar_print_caps()
349 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); in dmar_print_caps()
351 ecaphi = unit->hw_ecap >> 32; in dmar_print_caps()
352 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, in dmar_print_caps()
356 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), in dmar_print_caps()
357 DMAR_ECAP_IRO(unit->hw_ecap)); in dmar_print_caps()
371 unit->iommu.unit = device_get_unit(dev); in dmar_attach()
372 unit->iommu.dev = dev; in dmar_attach()
373 sysctl_ctx_init(&unit->iommu.sysctl_ctx); in dmar_attach()
374 dmaru = dmar_find_by_index(unit->iommu.unit); in dmar_attach()
377 unit->segment = dmaru->Segment; in dmar_attach()
378 unit->base = dmaru->Address; in dmar_attach()
379 unit->reg_rid = DMAR_REG_RID; in dmar_attach()
380 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, in dmar_attach()
381 &unit->reg_rid, RF_ACTIVE); in dmar_attach()
382 if (unit->regs == NULL) { in dmar_attach()
384 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
387 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); in dmar_attach()
388 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); in dmar_attach()
389 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); in dmar_attach()
393 unit->memdomain = acpi_get_domain(dev); in dmar_attach()
399 unit->x86c.intrs[i].irq = -1; in dmar_attach()
401 dmd = &unit->x86c.intrs[DMAR_INTR_FAULT]; in dmar_attach()
402 dmd->name = "fault"; in dmar_attach()
403 dmd->irq_rid = DMAR_FAULT_IRQ_RID; in dmar_attach()
404 dmd->handler = dmar_fault_intr; in dmar_attach()
405 dmd->msi_data_reg = DMAR_FEDATA_REG; in dmar_attach()
406 dmd->msi_addr_reg = DMAR_FEADDR_REG; in dmar_attach()
407 dmd->msi_uaddr_reg = DMAR_FEUADDR_REG; in dmar_attach()
408 dmd->enable_intr = dmar_enable_fault_intr; in dmar_attach()
409 dmd->disable_intr = dmar_disable_fault_intr; in dmar_attach()
413 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
416 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); in dmar_attach()
417 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); in dmar_attach()
418 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32); in dmar_attach()
421 dmd = &unit->x86c.intrs[DMAR_INTR_QI]; in dmar_attach()
422 dmd->name = "qi"; in dmar_attach()
423 dmd->irq_rid = DMAR_QI_IRQ_RID; in dmar_attach()
424 dmd->handler = dmar_qi_intr; in dmar_attach()
425 dmd->msi_data_reg = DMAR_IEDATA_REG; in dmar_attach()
426 dmd->msi_addr_reg = DMAR_IEADDR_REG; in dmar_attach()
427 dmd->msi_uaddr_reg = DMAR_IEUADDR_REG; in dmar_attach()
428 dmd->enable_intr = dmar_enable_qi_intr; in dmar_attach()
429 dmd->disable_intr = dmar_disable_qi_intr; in dmar_attach()
433 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
437 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data); in dmar_attach()
438 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr); in dmar_attach()
439 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32); in dmar_attach()
442 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); in dmar_attach()
443 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), in dmar_attach()
444 &unit->iommu.lock); in dmar_attach()
445 LIST_INIT(&unit->domains); in dmar_attach()
450 * domain-id value of zero is architecturally reserved. in dmar_attach()
451 * Software must not use domain-id value of zero in dmar_attach()
454 if ((unit->hw_cap & DMAR_CAP_CM) != 0) in dmar_attach()
455 alloc_unr_specific(unit->domids, 0); in dmar_attach()
457 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + in dmar_attach()
459 if (unit->memdomain != -1) { in dmar_attach()
460 unit->ctx_obj->domain.dr_policy = DOMAINSET_PREF( in dmar_attach()
461 unit->memdomain); in dmar_attach()
469 iommu_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); in dmar_attach()
475 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
482 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
485 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { in dmar_attach()
490 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
499 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
505 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
511 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
524 error = iommu_init_busdma(&unit->iommu); in dmar_attach()
527 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
537 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
632 for (depth--; depth != -1; depth--) { in dmar_dev_path()
677 if (devscope->Length < sizeof(*devscope)) { in dmar_match_devscope()
679 devscope->Length); in dmar_match_devscope()
680 return (-1); in dmar_match_devscope()
682 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && in dmar_match_devscope()
683 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) in dmar_match_devscope()
685 path_len = devscope->Length - sizeof(*devscope); in dmar_match_devscope()
688 devscope->Length); in dmar_match_devscope()
689 return (-1); in dmar_match_devscope()
695 devscope->Length); in dmar_match_devscope()
696 return (-1); in dmar_match_devscope()
699 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, in dmar_match_devscope()
700 dev_path, dev_path_len, devscope->EntryType)); in dmar_match_devscope()
712 dmarh = dmar_find_by_index(unit->iommu.unit); in dmar_match_by_path()
715 if (dmarh->Segment != dev_domain) in dmar_match_by_path()
717 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { in dmar_match_by_path()
723 ptrend = (char *)dmarh + dmarh->Header.Length; in dmar_match_by_path()
726 ptr += devscope->Length; in dmar_match_by_path()
729 if (match == -1) in dmar_match_by_path()
792 pci_get_function(dev), unit->iommu.unit, banner); in dmar_find()
797 iommu_device_set_iommu_prop(dev, unit->iommu.dev); in dmar_find()
824 ptrend = (char *)dmarh + dmarh->Header.Length; in dmar_find_nonpci()
829 ptr += devscope->Length; in dmar_find_nonpci()
830 if (devscope->EntryType != entry_type) in dmar_find_nonpci()
832 if (devscope->EnumerationId != id) in dmar_find_nonpci()
845 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) in dmar_find_nonpci()
850 *rid = PCI_RID(devscope->Bus, in dmar_find_nonpci()
851 path->Device, path->Function); in dmar_find_nonpci()
872 iommu_device_set_iommu_prop(dev, unit->iommu.dev); in dmar_find_hpet()
886 iommu_device_set_iommu_prop(apic_dev, unit->iommu.dev); in dmar_find_ioapic()
913 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) in dmar_rmrr_iter()
918 if (resmem->Segment != ria->dev_domain) in dmar_rmrr_iter()
922 ptrend = (char *)resmem + resmem->Header.Length; in dmar_rmrr_iter()
927 ptr += devscope->Length; in dmar_rmrr_iter()
928 match = dmar_match_devscope(devscope, ria->dev_busno, in dmar_rmrr_iter()
929 ria->dev_path, ria->dev_path_len); in dmar_rmrr_iter()
931 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain), in dmar_rmrr_iter()
933 entry->start = resmem->BaseAddress; in dmar_rmrr_iter()
935 entry->end = resmem->EndAddress; in dmar_rmrr_iter()
936 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, in dmar_rmrr_iter()
973 dev = pci_find_dbsf(segment, busno, path->Device, in dmar_path_dev()
974 path->Function); in dmar_path_dev()
975 if (i != path_len - 1) { in dmar_path_dev()
976 busno = pci_cfgregread(segment, busno, path->Device, in dmar_path_dev()
977 path->Function, PCIR_SECBUS_1, 1); in dmar_path_dev()
981 *rid = PCI_RID(busno, path->Device, path->Function); in dmar_path_dev()
1002 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) in dmar_inst_rmrr_iter()
1006 if (resmem->Segment != iria->dmar->segment) in dmar_inst_rmrr_iter()
1010 ptrend = (const char *)resmem + resmem->Header.Length; in dmar_inst_rmrr_iter()
1015 ptr += devscope->Length; in dmar_inst_rmrr_iter()
1017 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) in dmar_inst_rmrr_iter()
1020 dev_path_len = (devscope->Length - in dmar_inst_rmrr_iter()
1022 dev = dmar_path_dev(resmem->Segment, dev_path_len, in dmar_inst_rmrr_iter()
1023 devscope->Bus, in dmar_inst_rmrr_iter()
1029 iria->dmar->iommu.unit, in dmar_inst_rmrr_iter()
1030 (uintmax_t)resmem->BaseAddress, in dmar_inst_rmrr_iter()
1031 (uintmax_t)resmem->EndAddress, in dmar_inst_rmrr_iter()
1033 dmar_print_path(devscope->Bus, dev_path_len, in dmar_inst_rmrr_iter()
1037 unit = dmar_find_by_scope(resmem->Segment, in dmar_inst_rmrr_iter()
1038 devscope->Bus, in dmar_inst_rmrr_iter()
1041 if (iria->dmar != unit) in dmar_inst_rmrr_iter()
1043 dmar_get_ctx_for_devpath(iria->dmar, rid, in dmar_inst_rmrr_iter()
1044 resmem->Segment, devscope->Bus, in dmar_inst_rmrr_iter()
1049 if (iria->dmar != unit) in dmar_inst_rmrr_iter()
1051 iommu_instantiate_ctx(&(iria)->dmar->iommu, in dmar_inst_rmrr_iter()
1068 * Pre-create all contexts for the DMAR which have RMRR entries.
1086 if (!LIST_EMPTY(&dmar->domains)) { in dmar_instantiate_rmrr_ctxs()
1087 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, in dmar_instantiate_rmrr_ctxs()
1089 dmar->iommu.unit)); in dmar_instantiate_rmrr_ctxs()
1093 dmar->iommu.unit); in dmar_instantiate_rmrr_ctxs()
1098 dmar->iommu.unit); in dmar_instantiate_rmrr_ctxs()
1101 "error %d\n", dmar->iommu.unit, error); in dmar_instantiate_rmrr_ctxs()
1123 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, in dmar_print_domain()
1124 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt, in dmar_print_domain()
1125 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt); in dmar_print_domain()
1184 LIST_FOREACH(domain, &unit->domains, link) { in DB_SHOW_COMMAND_FLAGS()
1185 LIST_FOREACH(ctx, &domain->iodom.contexts, link) { in DB_SHOW_COMMAND_FLAGS()
1186 if (pci_domain == unit->segment && in DB_SHOW_COMMAND_FLAGS()
1187 bus == pci_get_bus(ctx->tag->owner) && in DB_SHOW_COMMAND_FLAGS()
1188 device == pci_get_slot(ctx->tag->owner) && in DB_SHOW_COMMAND_FLAGS()
1189 function == pci_get_function(ctx->tag-> in DB_SHOW_COMMAND_FLAGS()
1209 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit, in dmar_print_one()
1218 if (unit->ir_enabled) { in dmar_print_one()
1220 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); in dmar_print_one()
1227 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { in dmar_print_one()
1228 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; in dmar_print_one()
1238 if (unit->qi_enabled) { in dmar_print_one()
1243 (uintmax_t)unit->x86c.inv_queue, in dmar_print_one()
1245 (uintmax_t)unit->x86c.inv_queue_size, in dmar_print_one()
1248 unit->x86c.inv_queue_avail, in dmar_print_one()
1251 (uintmax_t)unit->x86c.inv_waitd_seq_hw, in dmar_print_one()
1252 &unit->x86c.inv_waitd_seq_hw, in dmar_print_one()
1253 (uintmax_t)unit->x86c.inv_waitd_seq_hw_phys, in dmar_print_one()
1254 unit->x86c.inv_waitd_seq, in dmar_print_one()
1255 unit->x86c.inv_waitd_gen); in dmar_print_one()
1262 LIST_FOREACH(domain, &unit->domains, link) { in dmar_print_one()
1305 return (&dmar->iommu); in dmar_find_method()
1314 return (&dmar->x86c); in dmar_get_x86_common()