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/linux/arch/powerpc/kernel/
H A Dcpu_specs_book3s_64.h203 { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
206 .cpu_name = "POWER6 (architected)",
214 { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
217 .cpu_name = "POWER7 (architected)",
229 { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
232 .cpu_name = "POWER8 (architected)",
259 { /* 3.00-compliant processor, i.e. Power9 "architected" mode */
262 .cpu_name = "POWER9 (architected)",
273 { /* 3.1-compliant processor, i.e. Power10 "architected" mode */
276 .cpu_name = "POWER10 (architected)",
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/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer.yaml7 title: ARM architected timer
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
17 The per-core architected timer is attached to a GIC to deliver its
95 supported for 32-bit systems which follow the ARMv7 architected reset
H A Darm,arch_timer_mmio.yaml7 title: ARM memory mapped architected timer
14 ARM cores may have a memory mapped architected timer, which provides up to 8
52 supported for 32-bit systems which follow the ARMv7 architected reset
/linux/arch/arm/mach-bcm/
H A DKconfig10 comment "IPROC architected SoCs"
24 This enables support for systems based on Broadcom IPROC architected SoCs.
87 comment "KONA architected SoCs"
/linux/Documentation/arch/arm64/
H A Damu.rst39 The Activity Monitors architecture provides space for up to 16 architected
41 implement additional architected event counters.
H A Delf_hwcaps.rst15 architected discovery mechanism available to userspace code at EL0. The
46 which are described by architected ID registers inaccessible to
/linux/arch/arm/kernel/
H A Darch_timer.c26 /* Use the architected timer for the delay loop. */ in arch_timer_delay_timer_register()
/linux/arch/alpha/include/asm/
H A Dhwrpb.h9 * These values are architected.
31 * These values are architected.
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Dcache.json539 …licDescription": "This event counts load uops with locked access retired to the architected path.",
550 …"PublicDescription": "This event counts line-splitted load uops retired to the architected path. A…
561 …"PublicDescription": "This event counts line-splitted store uops retired to the architected path. …
572 …tion": "This event counts load uops with true STLB miss retired to the architected path. True STLB…
583 …ion": "This event counts store uops with true STLB miss retired to the architected path. True STLB…
/linux/drivers/parisc/
H A Dgsc.h18 /* PA I/O Architected devices support at least 5 bits in the EIM register. */
/linux/Documentation/devicetree/bindings/perf/
H A Darm,smmu-v3-pmcg.yaml16 architected and IMPLEMENTATION DEFINED event counters.
/linux/arch/arm/mach-rockchip/
H A Drockchip.c29 * which is needed for the architected timer to work. in rockchip_timer_init()
/linux/arch/arm64/kernel/
H A Dtime.c66 panic("Unable to initialise architected timer.\n"); in time_init()
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Dcache.json539 …licDescription": "This event counts load uops with locked access retired to the architected path.",
550 …"PublicDescription": "This event counts line-splitted load uops retired to the architected path. A…
561 …"PublicDescription": "This event counts line-splitted store uops retired to the architected path. …
572 …tion": "This event counts load uops with true STLB miss retired to the architected path. True STLB…
583 …ion": "This event counts store uops with true STLB miss retired to the architected path. True STLB…
/linux/Documentation/virt/kvm/arm/
H A Dvcpu-features.rst18 Otherwise, all CPU features supported by KVM are described by the architected
/linux/arch/powerpc/include/asm/
H A Dcputhreads.h70 * architected, is not something a hypervisor could emulate and a future
H A Dlppaca.h108 * We are using a non architected field to determine if a partition is
/linux/Documentation/admin-guide/perf/
H A Dxgene-pmu.rst7 controller(s). These PMU devices are loosely architected to follow the
/linux/arch/powerpc/include/asm/nohash/
H A Dpte-e500.h12 /* Architected bits */
/linux/arch/alpha/include/uapi/asm/
H A Dfpu.h38 * floating-point enable bit (which is architected). On top of that,
/linux/include/scsi/
H A Dviosrp.h16 /* between partitions. The definitions in this file are architected, */
/linux/Documentation/arch/powerpc/
H A Delf_hwcaps.rst167 The processor supports architected PMU events in the range 0xE0-0xFF.
H A Dcxlflash.rst338 the kernel's knowledge. When encountered, the user's architected
353 architected behavior for a user is to call into this ioctl to recover
/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-qcom.c300 * Some platforms support more than the Arm SMMU architected maximum of in qcom_smmu_cfg_probe()
302 * groups don't exhibit the same behavior as the architected registers, in qcom_smmu_cfg_probe()
/linux/Documentation/devicetree/bindings/powerpc/
H A Dibm,powerpc-cpu-features.txt71 Node: A string describing an architected CPU feature, e.g., "floating-point".

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