| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | arm,arch_timer_mmio.yaml | 7 title: ARM memory mapped architected timer
14 ARM cores may have a memory mapped architected timer, which provides up to 8
52 supported for 32-bit systems which follow the ARMv7 architected reset
|
| /linux/arch/arm/mach-bcm/ |
| H A D | Kconfig | 10 comment "IPROC architected SoCs"
24 This enables support for systems based on Broadcom IPROC architected SoCs.
87 comment "KONA architected SoCs"
|
| /linux/arch/arm/kernel/ |
| H A D | arch_timer.c | 26 /* Use the architected timer for the delay loop. */ in arch_timer_delay_timer_register()
|
| /linux/arch/alpha/include/asm/ |
| H A D | hwrpb.h | 9 * These values are architected.
31 * These values are architected.
|
| /linux/drivers/parisc/ |
| H A D | gsc.h | 18 /* PA I/O Architected devices support at least 5 bits in the EIM register. */
|
| /linux/Documentation/devicetree/bindings/perf/ |
| H A D | arm,smmu-v3-pmcg.yaml | 16 architected and IMPLEMENTATION DEFINED event counters.
|
| /linux/arch/arm/mach-rockchip/ |
| H A D | rockchip.c | 29 * which is needed for the architected timer to work. in rockchip_timer_init()
|
| /linux/arch/arm64/kernel/ |
| H A D | time.c | 66 panic("Unable to initialise architected timer.\n"); in time_init()
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | cache.json | 539 "PublicDescription": "This event counts load uops with locked access retired to the architected path.",
550 "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
561 "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
572 "PublicDescription": "This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
583 "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
|
| /linux/Documentation/virt/kvm/arm/ |
| H A D | vcpu-features.rst | 18 Otherwise, all CPU features supported by KVM are described by the architected
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | cache.json | 539 "PublicDescription": "This event counts load uops with locked access retired to the architected path.",
550 "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
561 "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
572 "PublicDescription": "This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
583 "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
|
| /linux/arch/powerpc/include/asm/ |
| H A D | cputhreads.h | 70 * architected, is not something a hypervisor could emulate and a future
|
| H A D | lppaca.h | 108 * We are using a non architected field to determine if a partition is
|
| /linux/Documentation/admin-guide/perf/ |
| H A D | xgene-pmu.rst | 7 controller(s). These PMU devices are loosely architected to follow the
|
| /linux/arch/powerpc/include/asm/nohash/ |
| H A D | pte-e500.h | 12 /* Architected bits */
|
| /linux/include/scsi/ |
| H A D | viosrp.h | 16 /* between partitions. The definitions in this file are architected, */
|
| /linux/Documentation/arch/powerpc/ |
| H A D | elf_hwcaps.rst | 167 The processor supports architected PMU events in the range 0xE0-0xFF.
|
| /linux/Documentation/devicetree/bindings/powerpc/ |
| H A D | ibm,powerpc-cpu-features.txt | 71 Node: A string describing an architected CPU feature, e.g., "floating-point".
|
| /linux/arch/parisc/kernel/ |
| H A D | hpmc.S | 61 #define HPMC_PIM_DATA_SIZE 896 /* Enough to hold all architected 2.0 state */
|
| /linux/Documentation/PCI/ |
| H A D | acpi-info.rst | 50 These are all device-specific, non-architected things, so the only way a
|
| /linux/arch/powerpc/perf/ |
| H A D | generic-compat-pmu.c | 325 * From ISA v2.07 on, PMU features are architected; in init_generic_compat_pmu()
|
| /linux/include/linux/irqchip/ |
| H A D | arm-gic-v5.h | 29 * Architected PPIs
|
| /linux/arch/parisc/include/uapi/asm/ |
| H A D | pdc.h | 637 /* architected results from PDC_PIM/transfer hpmc on a PA1.1 machine */
661 * architected results from PDC_PIM/transfer hpmc on a PA2.0 machine
|
| /linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | cache.json | 506 "PublicDescription": "This event counts load uops with locked access retired to the architected path.",
517 "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
528 "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
539 "PublicDescription": "This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
550 "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
|
| /linux/drivers/pnp/ |
| H A D | quirks.c | 366 * MCHBAR is not an architected PCI BAR, so MCH space is usually in quirk_intel_mch()
|