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/linux/sound/pci/
H A Des1968.c35 * We only drive the APU/Wavecache as typical DACs and drive the
40 * Each APU can do a number of things, but we only really use
43 * is handed to the codec. One APU for mono, and a pair for stereo.
44 * When in stereo, the combination of smarts in the APU and Wavecache
49 * APU, through another rate converter APU, and then into memory via
72 * like the APU interface that is indirect registers gotten at through
296 /* APU Modes: reg 0x00, bit 4-7 */
319 /* APU Filtey Q Control */
397 /* APU Filter Control */
405 /* APU ATFP Type */
[all …]
/linux/Documentation/networking/devlink/
H A Dsfc.rst40 - SmartNIC application co-processor (APU) first stage boot loader version.
43 - SmartNIC application co-processor (APU) co-operating system loader version.
46 - SmartNIC application co-processor (APU) main operating system version.
49 - SmartNIC application co-processor (APU) recovery operating system version.
/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8365-clock.yaml16 - mediatek,mt8365-apu
38 apu: clock-controller@19020000 {
39 compatible = "mediatek,mt8365-apu", "syscon";
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi362 <&apu CLK_APU_IPU_CK>,
363 <&apu CLK_APU_AXI>,
364 <&apu CLK_APU_JTAG>,
365 <&apu CLK_APU_IF_CK>,
366 <&apu CLK_APU_EDMA>,
367 <&apu CLK_APU_AHB>;
368 clock-names = "apu", "apu-0",
369 "apu-1", "apu-2",
370 "apu-3", "apu-4",
371 "apu-5";
[all …]
/linux/drivers/platform/x86/
H A Dpcengines-apuv2.c78 { .name = "apu:green:1" },
79 { .name = "apu:green:2" },
80 { .name = "apu:green:3" },
133 /* Note: matching works on string prefix, so "apu2" must come before "apu" */
252 pr_err("failed to detect APU board via DMI\n"); in apu_board_init()
/linux/arch/powerpc/xmon/
H A Dppc.h125 /* Opcode is supported by e500x2 Integer select APU. */
131 /* Opcode is supported by branch locking APU. */
134 /* Opcode is supported by performance monitor APU. */
137 /* Opcode is supported by cache locking APU. */
140 /* Opcode is supported by machine check APU. */
185 /* Opcode is supported by Thread management APU */
391 /* Xilinx APU and FSL related operands */
/linux/drivers/media/pci/cx18/
H A Dcx18-mailbox.c20 static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
74 API_ENTRY(APU, CX18_APU_START, 0),
75 API_ENTRY(APU, CX18_APU_STOP, 0),
76 API_ENTRY(APU, CX18_APU_RESETAI, 0),
354 case APU: in epu_cmd()
355 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n", in epu_cmd()
389 case APU: in mb_ack_irq()
487 case APU: in epu_cmd_irq()
488 CX18_WARN("Unknown APU to EPU mailbox command %#0x\n", in epu_cmd_irq()
533 case APU: in cx18_api_epu_cmd_irq()
[all …]
H A Dcx18-scb.h86 /* Offset where to find the start of the APU code */
105 /* Offset to the mailbox used for sending commands from APU to CPU */
131 /* Fields for APU: */
H A Dcx18-firmware.c280 /* APU = SC or SC/2 = 125/62.5 */ in cx18_init_power()
366 #define CX18_APU_FIRMWARE "v4l-cx23418-apu.fw"
405 /* Start the CPU. The CPU will take care of the APU for us. */ in cx18_firmware_init()
409 /* Wait up to 500 ms for the APU to come out of reset */ in cx18_firmware_init()
H A Dcx23418.h48 /* Description: Command APU to start audio
54 /* Description: Command APU to stop audio
59 /* Description: Command APU to reset the AI
442 /* APU (Audio) mail box is corrupted */
/linux/drivers/clk/mediatek/
H A Dclk-mt8365-apu.c39 .compatible = "mediatek,mt8365-apu",
51 .name = "clk-mt8365-apu",
H A Dclk-mt8195-apusys_pll.c24 * No tuner control in apu pll, so set "tuner_XXX" as zero to imply it.
25 * No rst or post divider enable in apu pll, so set "rst_bar_mask" and "en_mask"
/linux/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp69 Only the APU along with all of its peripherals
101 application running in Linux, PMUFW will do APU only restart. If
129 the health of firmware not APU(Linux). Also, the external
186 of firmware not APU(Linux). Also, the external watchdog is
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsmuio_v11_0_6.c42 /* enable/disable ROM CG is not supported on APU */ in smuio_v11_0_6_update_rom_clock_gating()
63 /* CGTT_ROM_CLK_CTRL0 is not available for APU */ in smuio_v11_0_6_get_clock_gating_state()
H A Dsmuio_v11_0.c42 /* enable/disable ROM CG is not supported on APU */ in smuio_v11_0_update_rom_clock_gating()
66 /* CGTT_ROM_CLK_CTRL0 is not available for APU */ in smuio_v11_0_get_clock_gating_state()
H A Dsmuio_v13_0.c44 /* enable/disable ROM CG is not supported on APU */ in smuio_v13_0_update_rom_clock_gating()
65 /* CGTT_ROM_CLK_CTRL0 is not available for APU */ in smuio_v13_0_get_clock_gating_state()
/linux/Documentation/devicetree/bindings/bus/
H A Dxlnx,versal-net-cdx.yaml30 with which APU (Application Processor Unit) interacts to find out
48 phandle to the remoteproc_r5 rproc node using which APU interacts
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-ccp7 whether the CPU or APU has been fused to prevent tampering.
17 whether the AMD CPU or APU has been unlocked for debugging.
H A Dsysfs-amd-pmc13 APU/CPU models that can share the same firmware binary.
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu14_driver_if_v14_0_0.h187 …uint16_t SkinTemp; //Maximum skin temperature reported by APU and HS2 chassis se…
201 uint32_t ApuPower; //Time filtered APU power [mW]
204 uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW]
/linux/Documentation/gpu/amdgpu/
H A Ddriver-misc.rst53 Accelerated Processing Units (APU) Info
59 :file: ./apu-asic-info-table.csv
/linux/drivers/w1/masters/
H A Dds2482.c25 * The APU bit controls whether an active pullup (controlled slew-rate
27 * a 1-Wire line from low to high. When APU = 0, active pullup is disabled
39 MODULE_PARM_DESC(extra_config, "Extra Configuration settings 1=APU,2=PPM,3=SPU,8=1WS");
431 /* note: it seems like both SPU and APU have to be set! */ in ds2482_w1_set_pullup()
/linux/drivers/cdx/
H A DKconfig14 APU. CDX bus provides a mechanism for scanning and probing
/linux/drivers/platform/x86/amd/pmc/
H A DKconfig17 Say Y or M here if you have a notebook powered by AMD RYZEN CPU/APU.
/linux/arch/powerpc/kernel/
H A Dcpu_setup_44x.S45 /* enable APU between CPU and FPU */

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