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/linux/sound/pci/
H A Des1968.c35 * We only drive the APU/Wavecache as typical DACs and drive the
40 * Each APU can do a number of things, but we only really use
43 * is handed to the codec. One APU for mono, and a pair for stereo.
44 * When in stereo, the combination of smarts in the APU and Wavecache
49 * APU, through another rate converter APU, and then into memory via
72 * like the APU interface that is indirect registers gotten at through
296 /* APU Modes: reg 0x00, bit 4-7 */
319 /* APU Filtey Q Control */
397 /* APU Filte
450 u8 apu[4]; global() member
521 unsigned char apu[NR_APUS]; global() member
878 snd_es1968_apu_set_freq(struct es1968 * chip,int apu,int freq) snd_es1968_apu_set_freq() argument
887 snd_es1968_trigger_apu(struct es1968 * esm,int apu,int mode) snd_es1968_trigger_apu() argument
950 int channel, apu; snd_es1968_playback_setup() local
1051 int i, apu = es->apu[channel]; init_capture_apu() local
1454 int apu; snd_es1968_alloc_apu_pair() local
1469 snd_es1968_free_apu_pair(struct es1968 * chip,int apu) snd_es1968_free_apu_pair() argument
1639 int i, apu; es1968_measure_clock() local
[all...]
/linux/Documentation/networking/devlink/
H A Dsfc.rst44 - SmartNIC application co-processor (APU) first stage boot loader version.
47 - SmartNIC application co-processor (APU) co-operating system loader version.
50 - SmartNIC application co-processor (APU) main operating system version.
53 - SmartNIC application co-processor (APU) recovery operating system version.
/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8365-clock.yaml16 - mediatek,mt8365-apu
38 apu: clock-controller@19020000 {
39 compatible = "mediatek,mt8365-apu", "syscon";
/linux/arch/powerpc/xmon/
H A Dppc.h125 /* Opcode is supported by e500x2 Integer select APU. */
131 /* Opcode is supported by branch locking APU. */
134 /* Opcode is supported by performance monitor APU. */
137 /* Opcode is supported by cache locking APU. */
140 /* Opcode is supported by machine check APU. */
185 /* Opcode is supported by Thread management APU */
391 /* Xilinx APU and FSL related operands */
H A Dppc-opc.c860 /* Xilinx APU related masks and macros */
2875 /* An APU form instruction. */
2876 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1)) macro
2878 /* The mask for an APU form instruction. */
2879 #define APU_MASK APU (0x3f, 0x3ff, 1)
3292 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3315 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3326 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3328 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3357 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dxlnx,versal-net-ddrmc5.yaml26 phandle to the remoteproc_r5 rproc node using which APU interacts
27 with remote processor. APU primarily communicates with the RPU for
/linux/drivers/clk/mediatek/
H A Dclk-mt8365-apu.c39 .compatible = "mediatek,mt8365-apu",
51 .name = "clk-mt8365-apu",
/linux/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp69 Only the APU along with all of its peripherals
101 application running in Linux, PMUFW will do APU only restart. If
129 the health of firmware not APU(Linux). Also, the external
186 of firmware not APU(Linux). Also, the external watchdog is
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsmuio_v11_0_6.c42 /* enable/disable ROM CG is not supported on APU */ in smuio_v11_0_6_update_rom_clock_gating()
63 /* CGTT_ROM_CLK_CTRL0 is not available for APU */ in smuio_v11_0_6_get_clock_gating_state()
H A Dsmuio_v11_0.c42 /* enable/disable ROM CG is not supported on APU */ in smuio_v11_0_update_rom_clock_gating()
66 /* CGTT_ROM_CLK_CTRL0 is not available for APU */ in smuio_v11_0_get_clock_gating_state()
H A Dsmuio_v13_0.c44 /* enable/disable ROM CG is not supported on APU */ in smuio_v13_0_update_rom_clock_gating()
65 /* CGTT_ROM_CLK_CTRL0 is not available for APU */ in smuio_v13_0_get_clock_gating_state()
H A Dsmuio_v9_0.c42 /* enable/disable ROM CG is not supported on APU */ in smuio_v9_0_update_rom_clock_gating()
H A Dsmuio_v13_0_3.c82 * bit 1 == 1 APU form factor in smuio_v13_0_3_get_pkg_type()
/linux/Documentation/devicetree/bindings/bus/
H A Dxlnx,versal-net-cdx.yaml30 with which APU (Application Processor Unit) interacts to find out
48 phandle to the remoteproc_r5 rproc node using which APU interacts
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu15_driver_if_v15_0_0.h195 …uint16_t SkinTemp; //Maximum skin temperature reported by APU and HS2 chassis se…
209 uint32_t ApuPower; //Time filtered APU power [mW]
212 uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW]
/linux/drivers/gpu/drm/amd/include/
H A Dkgd_pp_interface.h257 * APU power is managed to system-level requirements through the PPT
260 * maximize APU performance within the system power budget.
285 * moving average of APU power (default ~5000 ms).
286 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
1423 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1473 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1523 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1576 uint16_t average_socket_power; // dGPU + APU power on A + A platform
1722 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */
1726 /* time filtered APU power [mW] */
/linux/Documentation/ABI/testing/
H A Dsysfs-amd-pmc13 APU/CPU models that can share the same firmware binary.
/linux/drivers/platform/x86/
H A Dasus-armoury.c249 pr_err("Refusing to set APU memory to unsafe value: 0x%x\n", value); in armoury_set_devstate()
688 /* Device memory available to APU */
691 * Values map for APU reserved memory (index + 1 number of GB).
725 pr_warn("Unrecognised value for APU mem 0x%08x\n", mem); in apu_mem_current_value_show()
749 pr_info("APU memory changed to %uGB, reboot required\n", requested + 1); in apu_mem_current_value_store()
762 ASUS_ATTR_GROUP_ENUM(apu_mem, "apu_mem", "Set available system RAM (in GB) for the APU to use");
796 "Set the APU package limit");
/linux/drivers/edac/
H A Dversalnet_edac.c677 case 123: err_str = "err_int_irq from APU GIC Distributor"; break; in rpmsg_cb()
678 case 124: err_str = "fault_int_irq from APU GIC Distribute"; break; in rpmsg_cb()
680 case 140: err_str = "APU Cluster 0 error"; break; in rpmsg_cb()
681 case 141: err_str = "APU Cluster 1 error"; break; in rpmsg_cb()
682 case 142: err_str = "APU Cluster 2 error"; break; in rpmsg_cb()
683 case 143: err_str = "APU Cluster 3 error"; break; in rpmsg_cb()
/linux/arch/powerpc/kernel/
H A Dcpu_setup_44x.S45 /* enable APU between CPU and FPU */
/linux/Documentation/devicetree/bindings/iommu/
H A Dmediatek,iommu.yaml85 - mediatek,mt8189-iommu-apu # generation two
217 - mediatek,mt8189-iommu-apu
/linux/drivers/cdx/controller/
H A Dmcdi_functions.h78 * it is the responsibility of the entity managing the IOMMU (APU kernel)
H A Dmc_cdx_pcol.h251 * Application Processors (APUs). As such, they only apply to the PSX APU side,
316 * are equivalent to APU physical addresses. Implementation note - for this to
660 * of the entity managing the IOMMU (APU kernel) to supply the correct IOVA
/linux/drivers/platform/x86/amd/pmf/
H A Dsps.c110 pr_debug("PPT APU[%d] = %u\n", i, info->val[i].ppt_pmf_apu_only); in amd_pmf_dump_apts_sps_defaults()
112 pr_debug("STT APU[%d] = %u\n", i, info->val[i].stt_skin_temp_limit_apu); in amd_pmf_dump_apts_sps_defaults()
/linux/arch/powerpc/include/asm/
H A Dreg_fsl_emb.h37 /* Freescale Book E Performance Monitor APU Registers */

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