Home
last modified time | relevance | path

Searched full:apu (Results 1 – 25 of 64) sorted by relevance

123

/linux/Documentation/networking/devlink/
H A Dsfc.rst44 - SmartNIC application co-processor (APU) first stage boot loader version.
47 - SmartNIC application co-processor (APU) co-operating system loader version.
50 - SmartNIC application co-processor (APU) main operating system version.
53 - SmartNIC application co-processor (APU) recovery operating system version.
/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8365-clock.yaml16 - mediatek,mt8365-apu
38 apu: clock-controller@19020000 {
39 compatible = "mediatek,mt8365-apu", "syscon";
/linux/arch/powerpc/xmon/
H A Dppc.h125 /* Opcode is supported by e500x2 Integer select APU. */
131 /* Opcode is supported by branch locking APU. */
134 /* Opcode is supported by performance monitor APU. */
137 /* Opcode is supported by cache locking APU. */
140 /* Opcode is supported by machine check APU. */
185 /* Opcode is supported by Thread management APU */
391 /* Xilinx APU and FSL related operands */
H A Dppc-opc.c860 /* Xilinx APU related masks and macros */
2875 /* An APU form instruction. */
2876 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1)) macro
2878 /* The mask for an APU form instruction. */
2879 #define APU_MASK APU (0x3f, 0x3ff, 1)
3292 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3315 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3326 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3328 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3357 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi417 <&apu CLK_APU_IPU_CK>,
418 <&apu CLK_APU_AXI>,
419 <&apu CLK_APU_JTAG>,
420 <&apu CLK_APU_IF_CK>,
421 <&apu CLK_APU_EDMA>,
422 <&apu CLK_APU_AHB>;
423 clock-names = "apu", "apu-0",
424 "apu-1", "apu-2",
425 "apu-3", "apu-4",
426 "apu-5";
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dxlnx,versal-net-ddrmc5.yaml26 phandle to the remoteproc_r5 rproc node using which APU interacts
27 with remote processor. APU primarily communicates with the RPU for
/linux/drivers/clk/mediatek/
H A Dclk-mt8365-apu.c39 .compatible = "mediatek,mt8365-apu",
51 .name = "clk-mt8365-apu",
H A Dclk-mt8195-apusys_pll.c24 * No tuner control in apu pll, so set "tuner_XXX" as zero to imply it.
25 * No rst or post divider enable in apu pll, so set "rst_bar_mask" and "en_mask"
/linux/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp69 Only the APU along with all of its peripherals
101 application running in Linux, PMUFW will do APU only restart. If
129 the health of firmware not APU(Linux). Also, the external
186 of firmware not APU(Linux). Also, the external watchdog is
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsmuio_v11_0_6.c42 /* enable/disable ROM CG is not supported on APU */ in smuio_v11_0_6_update_rom_clock_gating()
63 /* CGTT_ROM_CLK_CTRL0 is not available for APU */ in smuio_v11_0_6_get_clock_gating_state()
H A Dsmuio_v11_0.c42 /* enable/disable ROM CG is not supported on APU */ in smuio_v11_0_update_rom_clock_gating()
66 /* CGTT_ROM_CLK_CTRL0 is not available for APU */ in smuio_v11_0_get_clock_gating_state()
H A Dsmuio_v13_0.c44 /* enable/disable ROM CG is not supported on APU */ in smuio_v13_0_update_rom_clock_gating()
65 /* CGTT_ROM_CLK_CTRL0 is not available for APU */ in smuio_v13_0_get_clock_gating_state()
H A Dsmuio_v9_0.c42 /* enable/disable ROM CG is not supported on APU */ in smuio_v9_0_update_rom_clock_gating()
H A Dsmuio_v13_0_3.c82 * bit 1 == 1 APU form factor in smuio_v13_0_3_get_pkg_type()
/linux/Documentation/devicetree/bindings/bus/
H A Dxlnx,versal-net-cdx.yaml30 with which APU (Application Processor Unit) interacts to find out
48 phandle to the remoteproc_r5 rproc node using which APU interacts
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-ccp7 whether the CPU or APU has been fused to prevent tampering.
17 whether the AMD CPU or APU has been unlocked for debugging.
H A Dsysfs-amd-pmc13 APU/CPU models that can share the same firmware binary.
/linux/drivers/platform/x86/
H A Dasus-armoury.c230 pr_err("Refusing to set APU memory to unsafe value: 0x%x\n", value); in armoury_set_devstate()
661 /* Device memory available to APU */
664 * Values map for APU reserved memory (index + 1 number of GB).
698 pr_warn("Unrecognised value for APU mem 0x%08x\n", mem); in apu_mem_current_value_show()
722 pr_info("APU memory changed to %uGB, reboot required\n", requested + 1); in apu_mem_current_value_store()
735 ASUS_ATTR_GROUP_ENUM(apu_mem, "apu_mem", "Set available system RAM (in GB) for the APU to use");
769 "Set the APU package limit");
/linux/drivers/edac/
H A Dversalnet_edac.c675 case 123: err_str = "err_int_irq from APU GIC Distributor"; break; in rpmsg_cb()
676 case 124: err_str = "fault_int_irq from APU GIC Distribute"; break; in rpmsg_cb()
678 case 140: err_str = "APU Cluster 0 error"; break; in rpmsg_cb()
679 case 141: err_str = "APU Cluster 1 error"; break; in rpmsg_cb()
680 case 142: err_str = "APU Cluster 2 error"; break; in rpmsg_cb()
681 case 143: err_str = "APU Cluster 3 error"; break; in rpmsg_cb()
/linux/Documentation/devicetree/bindings/iommu/
H A Dmediatek,iommu.yaml85 - mediatek,mt8189-iommu-apu # generation two
217 - mediatek,mt8189-iommu-apu
/linux/arch/powerpc/kernel/
H A Dcpu_setup_44x.S45 /* enable APU between CPU and FPU */
/linux/drivers/cdx/
H A Dcdx.c22 * | Application CPUs (APU) |
51 * image and implements a mechanism that allows the APU drivers to
54 * discover, reset and rescan of the FPGA devices for the APU. This is
55 * done using memory mapped interface provided by the RPU to APU.
/linux/drivers/platform/x86/amd/pmf/
H A Dsps.c110 pr_debug("PPT APU[%d] = %u\n", i, info->val[i].ppt_pmf_apu_only); in amd_pmf_dump_apts_sps_defaults()
112 pr_debug("STT APU[%d] = %u\n", i, info->val[i].stt_skin_temp_limit_apu); in amd_pmf_dump_apts_sps_defaults()
/linux/drivers/cdx/controller/
H A Dmcdi_functions.h78 * it is the responsibility of the entity managing the IOMMU (APU kernel)
H A Dmc_cdx_pcol.h251 * Application Processors (APUs). As such, they only apply to the PSX APU side,
316 * are equivalent to APU physical addresses. Implementation note - for this to
660 * of the entity managing the IOMMU (APU kernel) to supply the correct IOVA

123