xref: /linux/Documentation/devicetree/bindings/iommu/qcom,iommu.yaml (revision ce5cfb0fa20dc6454da039612e34325b7b4a8243) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies legacy IOMMU implementations
8
9maintainers:
10  - Konrad Dybcio <konradybcio@kernel.org>
11
12description: |
13  Qualcomm "B" family devices which are not compatible with arm-smmu have
14  a similar looking IOMMU, but without access to the global register space
15  and optionally requiring additional configuration to route context IRQs
16  to non-secure vs secure interrupt line.
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - enum:
23              - qcom,msm8916-iommu
24              - qcom,msm8917-iommu
25              - qcom,msm8937-iommu
26              - qcom,msm8953-iommu
27          - const: qcom,msm-iommu-v1
28      - items:
29          - enum:
30              - qcom,msm8953-iommu
31              - qcom,msm8976-iommu
32          - const: qcom,msm-iommu-v2
33
34  clocks:
35    minItems: 2
36    items:
37      - description: Clock required for IOMMU register group access
38      - description: Clock required for underlying bus access
39      - description: Clock required for Translation Buffer Unit access
40
41  clock-names:
42    minItems: 2
43    items:
44      - const: iface
45      - const: bus
46      - const: tbu
47
48  power-domains:
49    maxItems: 1
50
51  reg:
52    maxItems: 1
53
54  ranges: true
55
56  qcom,iommu-secure-id:
57    $ref: /schemas/types.yaml#/definitions/uint32
58    description:
59      The SCM secure ID of the IOMMU instance.
60
61  '#address-cells':
62    const: 1
63
64  '#size-cells':
65    const: 1
66
67  '#iommu-cells':
68    const: 1
69
70patternProperties:
71  "^iommu-ctx@[0-9a-f]+$":
72    type: object
73    additionalProperties: false
74    properties:
75      compatible:
76        enum:
77          - qcom,msm-iommu-v1-ns
78          - qcom,msm-iommu-v1-sec
79          - qcom,msm-iommu-v2-ns
80          - qcom,msm-iommu-v2-sec
81
82      interrupts:
83        maxItems: 1
84
85      reg:
86        maxItems: 1
87
88      qcom,ctx-asid:
89        $ref: /schemas/types.yaml#/definitions/uint32
90        description:
91          The ASID number associated to the context bank.
92
93    required:
94      - compatible
95      - interrupts
96      - reg
97
98required:
99  - compatible
100  - clocks
101  - clock-names
102  - ranges
103  - '#address-cells'
104  - '#size-cells'
105  - '#iommu-cells'
106
107additionalProperties: false
108
109examples:
110  - |
111    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
112    #include <dt-bindings/interrupt-controller/arm-gic.h>
113
114    apps_iommu: iommu@1e20000 {
115      compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
116      reg = <0x01ef0000 0x3000>;
117      clocks = <&gcc GCC_SMMU_CFG_CLK>,
118               <&gcc GCC_APSS_TCU_CLK>;
119      clock-names = "iface", "bus";
120      qcom,iommu-secure-id = <17>;
121      #address-cells = <1>;
122      #size-cells = <1>;
123      #iommu-cells = <1>;
124      ranges = <0 0x01e20000 0x40000>;
125
126      /* mdp_0: */
127      iommu-ctx@4000 {
128        compatible = "qcom,msm-iommu-v1-ns";
129        reg = <0x4000 0x1000>;
130        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
131      };
132    };
133