Home
last modified time | relevance | path

Searched +full:ap806 +full:- +full:sei (Results 1 – 6 of 6) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmarvell,ap806-sei.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-sei.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell SEI (System Error Interrupt) Controller
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 Marvell SEI (System Error Interrupt) controller is an interrupt aggregator. It
22 const: marvell,ap806-sei
30 '#interrupt-cells':
33 interrupt-controller: true
[all …]
H A Dmarvell,sei.txt1 Marvell SEI (System Error Interrupt) Controller
2 -----------------------------------------------
4 Marvell SEI (System Error Interrupt) controller is an interrupt
15 - compatible: should be one of:
16 * "marvell,ap806-sei"
17 - reg: SEI registers location and length.
18 - interrupts: identifies the parent IRQ that will be triggered.
19 - #interrupt-cells: number of cells to define an SEI wired interrupt
22 - interrupt-controller: identifies the node as an interrupt controller
24 - msi-controller: identifies the node as an MSI controller for the CPs
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/
H A Dap80x-system-controller.txt4 The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
21 The Device Tree node representing the AP806/AP807 system controller
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/freebsd/sys/arm64/conf/
H A Dstd.marvell20 device mv_ap806_gicp # Marvell AP806 GICP
21 device mv_ap806_sei # Marvell AP806 SEI
23 # Real-time clock support
24 device mv_rtc # Marvell Real-time Clock
27 device safexcel # Inside Secure EIP-97
37 device uart_ns8250 # ns8250-type UART driver
58 device a37x0_xtal # Marvell xtal-clock
59 device a37x0_tbg # Marvell tbg-clock
60 device a37x0_nb_periph # Marvell north-bridge peripheral clock
61 device a37x0_sb_periph # Maravell south-bridge peripheral clock
/freebsd/sys/arm/mv/
H A Dmv_ap806_sei.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
53 #define MV_AP806_SEI_LOCK(_sc) mtx_lock(&(_sc)->mtx)
54 #define MV_AP806_SEI_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
55 #define MV_AP806_SEI_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \
56 device_get_nameunit(_sc->dev), "mv_ap806_sei", MTX_DEF)
57 #define MV_AP806_SEI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx);
58 #define MV_AP806_SEI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
59 #define MV_AP806_SEI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED);
98 {"marvell,ap806-sei", 1},
[all …]