Searched +full:am4376 +full:- +full:pruss (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: TI PRU-ICSS Local Interrupt Controller10 - Suman Anna <s-anna@ti.com>13 Each PRU-ICSS has a single interrupt controller instance that is common17 various other PRUSS internal and external peripherals. The first 2 output20 including the MPU and/or other PRUSS instances, DSPs or devices.22 The property "ti,irqs-reserved" is used for denoting the connection[all …]
1 // SPDX-License-Identifier: GPL-2.0-only5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/8 #include <dt-bindings/bus/ti-sysc.h>9 #include <dt-bindings/gpio/gpio.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/clock/am4.h>15 interrupt-parent = <&wakeupgen>;16 #address-cells = <1>;17 #size-cells = <1>;41 #address-cells = <1>;[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Suman Anna <s-anna@ti.com>13 Each Programmable Real-Time Unit and Industrial Communication Subsystem14 (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called15 Programmable Real-Time Units (PRUs), each represented by a node. Each PRU17 use the Data RAMs present within the PRU-ICSS for code execution.27 corresponding PRU-ICSS node. Each node can optionally be rendered inactive by[all …]