| /linux/Documentation/arch/x86/ |
| H A D | zero-page.rst | 16 000/040 ALL screen_info Text mode or frame buffer information
18 040/014 ALL apm_bios_info APM BIOS information (struct apm_bios_info)
19 058/008 ALL tboot_addr Physical address of tboot shared page
20 060/010 ALL ist_info Intel SpeedStep (IST) BIOS support information
22 070/008 ALL acpi_rsdp_addr Physical address of ACPI RSDP table
23 080/010 ALL hd0_info hd0 disk parameter, OBSOLETE!!
24 090/010 ALL hd1_info hd1 disk parameter, OBSOLETE!!
25 0A0/010 ALL sys_desc_table System description table (struct sys_desc_table),
27 0B0/010 ALL olpc_ofw_header OLPC's OpenFirmware CIF and friends
28 0C0/004 ALL ext_ramdisk_image ramdisk_image high 32bits
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | recommended.json | 12 "BriefDescription": "All data cache accesses.",
17 "BriefDescription": "All L2 cache accesses.",
18 …r": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l…
36 "MetricExpr": "l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
41 "BriefDescription": "All L2 cache misses.",
42 …etricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
60 "MetricExpr": "l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
65 "BriefDescription": "All L2 cache hits.",
66 "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.all",
84 "MetricExpr": "l2_pf_hit_l2.all",
[all …]
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| /linux/include/net/netfilter/ |
| H A D | nf_conntrack_tuple.h | 26 #define NF_CT_TUPLE_L3SIZE ARRAY_SIZE(((union nf_inet_addr *)NULL)->all)
45 __be16 all; member
90 &t->src.u3.ip, ntohs(t->src.u.all), in nf_ct_dump_tuple_ip()
91 &t->dst.u3.ip, ntohs(t->dst.u.all)); in nf_ct_dump_tuple_ip()
100 t->src.u3.all, ntohs(t->src.u.all), in nf_ct_dump_tuple_ipv6()
101 t->dst.u3.all, ntohs(t->dst.u.all)); in nf_ct_dump_tuple_ipv6()
131 t1->src.u.all == t2->src.u.all && in __nf_ct_tuple_src_equal()
139 t1->dst.u.all == t2->dst.u.all && in __nf_ct_tuple_dst_equal()
155 m1->src.u.all == m2->src.u.all); in nf_ct_tuple_mask_equal()
166 if ((t1->src.u3.all[count] ^ t2->src.u3.all[count]) & in nf_ct_tuple_src_mask_cmp()
[all …]
|
| /linux/Documentation/userspace-api/ioctl/ |
| H A D | ioctl-number.rst | 45 convention at all.
77 0x02 all linux/fd.h
78 0x03 all linux/hdreg.h
80 0x06 all linux/lp.h
82 0x09 all linux/raid/md_u.h
86 0x12 all linux/fs.h BLK* ioctls
88 0x15 all linux/fs.h FS_IOC_* ioctls
89 0x1b all InfiniBand Subsystem
91 0x20 all drivers/cdrom/cm206.h
92 0x22 all scsi/sg.h
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/ |
| H A D | pipeline.json | 21 "PublicDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy",
24 "BriefDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy"
27 …scription": "Duration for which all slots in the load-store issue queue are busy. This event count…
30 …scription": "Duration for which all slots in the load-store issue queue are busy. This event count…
33 …ription": "Duration for which all slots in the data processing issue queue are busy. This event co…
36 …ription": "Duration for which all slots in the data processing issue queue are busy. This event co…
39 …"PublicDescription": "Duration for which all slots in the data engine issue queue are busy. This e…
42 …"BriefDescription": "Duration for which all slots in the data engine issue queue are busy. This ev…
|
| /linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | memory.json | 215 "BriefDescription": "Counts all demand & prefetch data reads",
225 "BriefDescription": "Counts all demand & prefetch data reads",
235 "BriefDescription": "Counts all demand & prefetch data reads",
245 "BriefDescription": "Counts all demand & prefetch data reads",
255 "BriefDescription": "Counts all demand & prefetch data reads",
265 "BriefDescription": "Counts all demand & prefetch data reads",
275 "BriefDescription": "Counts all demand & prefetch data reads",
285 "BriefDescription": "Counts all demand & prefetch data reads",
295 "BriefDescription": "Counts all demand & prefetch data reads",
305 "BriefDescription": "Counts all demand & prefetch data reads",
[all …]
|
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
37 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
46 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
51 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
56 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
61 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
66 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
71 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
86 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
[all …]
|
| H A D | cache.json | 62 "EventName": "L2_LINES_IN.ALL",
207 "BriefDescription": "All requests that miss L2 cache.",
215 "BriefDescription": "All L2 requests.",
483 …"PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PR…
494 "PublicDescription": "Counts all retired store uops.",
559 …"PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads in…
568 …sactions reached the super queue including requests initiated by the core, all L3 prefetches, page…
700 "BriefDescription": "Counts all demand & prefetch data reads have any response type.",
710 "BriefDescription": "Counts all demand & prefetch data reads",
720 "BriefDescription": "Counts all demand & prefetch data reads",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
37 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
46 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
51 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
56 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
61 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
66 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
71 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
86 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | virtual-memory.json | 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
8 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
37 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
46 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
51 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
56 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
61 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
66 …"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a pa…
71 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
86 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
[all …]
|
| /linux/tools/testing/selftests/tc-testing/tc-tests/filters/ |
| H A D | matchall.json | 180 …"name": "Add ingress matchall filter for all protocols and action CONTINUE with handle at 32-bit m…
191 … "$TC filter add dev $DUMMY parent ffff: handle 0xffffffff prio 1 protocol all matchall action con…
193 …"verifyCmd": "$TC filter get dev $DUMMY parent ffff: handle 0xffffffff prio 1 protocol all matchal…
194 …"matchPattern": "^filter parent ffff: protocol all pref 1 matchall.*handle 0xffffffff.*gact action…
202 …"name": "Add egress matchall filter for all protocols and action CONTINUE with handle at 32-bit ma…
213 …"cmdUnderTest": "$TC filter add dev $DUMMY parent 1: handle 0xffffffff prio 1 protocol all matchal…
215 … "verifyCmd": "$TC filter get dev $DUMMY parent 1: handle 0xffffffff prio 1 protocol all matchall",
216 …"matchPattern": "^filter parent 1: protocol all pref 1 matchall.*handle 0xffffffff.*gact action co…
224 … "name": "Add ingress matchall filter for all protocols and action RECLASSIFY with skip_hw flag",
235 …"cmdUnderTest": "$TC filter add dev $DUMMY parent ffff: handle 0x1 prio 1 protocol all matchall sk…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | cache.json | 75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
105 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
111 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
134 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
140 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
146 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | virtual-memory.json | 7 …ue to loads (including SW prefetches) whose address translations missed in all Translation Lookasi…
13 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
17 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. T…
27 …of page walks completed due to stores whose address translations missed in all Translation Lookasi…
33 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s…
37 …"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. …
47 … completed due to instruction fetches whose address translations missed in all Translation Lookasi…
53 …"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page size…
57 …"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This im…
|
| /linux/Documentation/admin-guide/cgroup-v1/ |
| H A D | devices.rst | 11 'type' is a (all), c (char), or b (block). 'all' means it applies
12 to all types and all major and minor numbers. Major and minor are
13 either an integer or * for all. Access is a composition of r
16 The root device cgroup starts with rwm to 'all'. A child device
62 a cgroup's devices.deny file, all its children will have that entry removed
63 from their whitelist and all the locally set whitelist entries will be
85 A all "b 8:* rwm", "c 116:* rw"
86 B "c 1:3 rwm", "b 3:* rwm" all the rest
98 A "c 1:3 rwm", "c 1:5 r" all the rest
99 B "c 1:3 rwm", "c 1:5 r" all the rest
[all …]
|
| /linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | memory.json | 5 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data …
6 … and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand…
65 … "BriefDescription": "Pump prediction correct. Counts across all types of pumps for a demand load",
71 "BriefDescription": "Pump misprediction. Counts across all types of pumps for a demand load",
72 "PublicDescription": "Pump Mis prediction Counts across all types of pumpsfor a demand load"
113 …and Final Pump Scope and data sourced across this scope was group pump for all data types excludin…
119 …cope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excludin…
125 …inal Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excludin…
126 …p Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excludin…
185 …"BriefDescription": "Pump prediction correct. Counts across all types of pumps for all data types …
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen3/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/tigerlake/ |
| H A D | uncore-memory.json | 3 …every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests res…
12 … 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each wri…
21 …very write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests res…
30 …every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests res…
39 … 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each wri…
48 …very write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests res…
|
| H A D | uncore-interconnect.json | 3 "BriefDescription": "UNC_ARB_COH_TRK_REQUESTS.ALL",
6 "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",
15 "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL",
43 … "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL",
47 "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL",
64 …"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This ev…
74 …"BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry i…
77 "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
93 "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL",
96 "EventName": "UNC_ARB_TRK_REQUESTS.ALL",
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen2/ |
| H A D | cache.json | 5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
|
| /linux/tools/perf/ |
| H A D | builtin-bench.c | 42 { "all", "Run all NUMA benchmarks", NULL },
51 { "all", "Run all scheduler benchmarks", NULL },
60 { "all", "Run all syscall benchmarks", NULL },
68 { "all", "Run all memory access benchmarks", NULL },
79 { "all", "Run all fute
[all...] |
| /linux/drivers/cpuidle/ |
| H A D | coupled.c | 36 * WFI state until all cpus are ready to enter a coupled state, at
37 * which point the coupled state function will be called on all
40 * Once all cpus are ready to enter idle, they are woken by an smp
43 * final pass is needed to guarantee that all cpus will call the
56 * and only read after all the cpus are ready for the coupled idle
68 * Set struct cpuidle_device.coupled_cpus to the mask of all
69 * coupled cpus, usually the same as cpu_possible_mask if all cpus
81 * called on all cpus at approximately the same time. The driver
82 * should ensure that the cpus all abort together if any cpu tries
132 * cpuidle_coupled_parallel_barrier - synchronize all online coupled cpus
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 8 …xecuting instructions long before the branch true execution path is known. All branches utilize th…
17 …all taken branch instructions retired. Branch prediction predicts the branch target and enables t…
27 …xecuting instructions long before the branch true execution path is known. All branches utilize th…
37 …xecuting instructions long before the branch true execution path is known. All branches utilize th…
47 …xecuting instructions long before the branch true execution path is known. All branches utilize th…
57 …xecuting instructions long before the branch true execution path is known. All branches utilize th…
67 …xecuting instructions long before the branch true execution path is known. All branches utilize th…
77 …xecuting instructions long before the branch true execution path is known. All branches utilize th…
87 …xecuting instructions long before the branch true execution path is known. All branches utilize th…
97 …xecuting instructions long before the branch true execution path is known. All branches utilize th…
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/ |
| H A D | pipeline.json | 15 "PublicDescription": "Duration for which all slots in the Load-Store Unit are busy",
18 "BriefDescription": "Duration for which all slots in the Load-Store Unit are busy"
21 "PublicDescription": "Duration for which all slots in the load-store issue queue are busy",
24 "BriefDescription": "Duration for which all slots in the load-store issue queue are busy"
27 … "PublicDescription": "Duration for which all slots in the data processing issue queue are busy",
30 … "BriefDescription": "Duration for which all slots in the data processing issue queue are busy"
33 "PublicDescription": "Duration for which all slots in the Data Engine issue queue are busy",
36 "BriefDescription": "Duration for which all slots in the Data Engine issue queue are busy"
|
| /linux/Documentation/process/ |
| H A D | submit-checklist.rst | 10 These are all above and beyond the documentation that is provided in
24 3) All memory barriers {e.g., ``barrier()``, ``rmb()``, ``wmb()``} need a
35 2) All new ``Kconfig`` options have help text.
47 2) All new ``/proc`` entries are documented under ``Documentation/``
49 3) All new kernel boot parameters are documented in
52 4) All new module parameters are documented with ``MODULE_PARM_DESC()``
54 5) All new userspace interfaces are documented in ``Documentation/ABI/``.
67 You should be able to justify all violations that remain in
105 and/or ``=m`` (if that option is available) [not all of these at the
118 ``CONFIG_PROVE_RCU`` and ``CONFIG_DEBUG_OBJECTS_RCU_HEAD`` all
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | cache.json | 53 "EventName": "L2_LINES_IN.ALL",
182 "BriefDescription": "All requests that miss L2 cache",
186 "PublicDescription": "All requests that miss L2 cache.",
209 "BriefDescription": "All L2 requests",
213 "PublicDescription": "All L2 requests.",
250 …lative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.",
260 …tive accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3.…
271 …"PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch in…
282 "PublicDescription": "Counts all retired store instructions.",
287 "BriefDescription": "All retired memory instructions.",
[all …]
|