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/linux/Documentation/devicetree/bindings/ata/
H A Dahci-platform.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
13 It is possible, but not required, to represent each port as a sub-node.
14 It allows to enable each port independently when dealing with multiple
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
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H A Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial ATA AHCI controllers
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
14 This document defines device tree properties for a common AHCI SATA
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
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H A Dsnps,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller.
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
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H A Dsnps,dwc-ahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller properties
10 - Serge Semin <fancer.lancer@gmail.com>
14 AHCI controller properties.
19 - $ref: ahci-common.yaml#
30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
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H A Dbrcm,sata-brcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SATA3 AHCI Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
14 - Florian Fainelli <f.fainelli@gmail.com>
17 - $ref: ahci-common.yaml#
22 - items:
23 - enum:
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H A Dbaikal,bt1-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
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H A Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ceva AHCI SATA Controller
10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
13 The Ceva SATA controller mostly conforms to the AHCI interface with some
14 special extensions to add functionality, is a high-performance dual-port
15 SATA host controller with an AHCI compliant command layer which supports
17 structure (FIS) based switching for systems employing port multipliers.
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H A Dsata_highbank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda AHCI SATA Controller
10 The Calxeda SATA controller mostly conforms to the AHCI interface
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
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/linux/drivers/ata/
H A Dlibahci_platform.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AHCI SATA platform library
5 * Copyright 2004-2005 Red Hat, Inc.
26 #include "ahci.h"
37 * ahci_platform_enable_phys - Enable PHYs
40 * This function enables all the PHYs found in hpriv->phys, if any.
51 for (i = 0; i < hpriv->nports; i++) { in ahci_platform_enable_phys()
55 rc = phy_init(hpriv->phys[i]); in ahci_platform_enable_phys()
59 rc = phy_set_mode(hpriv->phys[i], PHY_MODE_SATA); in ahci_platform_enable_phys()
61 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
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H A Dahci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ahci.c - AHCI SATA support
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
25 #include <linux/dma-mapping.h>
32 #include <linux/ahci-remap.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include "ahci.h"
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
10 uses pata-platform driver to enable the relevant driver in the
21 If you want to use an ATA hard disk, ATA tape drive, ATA CD-ROM or
62 <file:Documentation/admin-guide/kernel-parameters.txt>.
76 This option adds support for ATA-related ACPI objects.
98 bool "SATA Port Multiplier support"
102 This option adds support for SATA Port Multipliers
107 comment "Controllers with non-SFF native interface"
110 tristate "AHCI SATA support"
114 This option enables support for AHCI Serial ATA.
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H A Dahci_brcm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom SATA3 AHCI Controller Driver
5 * Copyright © 2009-2015 Broadcom Corporation
22 #include "ahci.h"
24 #define DRV_NAME "brcm-ahci"
28 #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
29 #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
30 #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
51 /* On big-endian MIPS, buses are reversed to big endian, so switch them back */
53 #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
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H A Dahci_dm816.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DaVinci DM816 AHCI SATA platform driver
16 #include "ahci.h"
18 #define AHCI_DM816_DRV_NAME "ahci-dm816"
55 * We should have divided evenly - if not, return an invalid in ahci_dm816_get_mpy_bits()
58 return -1; in ahci_dm816_get_mpy_bits()
69 * keep-alive clock and the external reference clock. We need the in ahci_dm816_phy_init()
72 if (hpriv->n_clks < 2) { in ahci_dm816_phy_init()
74 return -EINVAL; in ahci_dm816_phy_init()
77 refclk_rate = clk_get_rate(hpriv->clks[1].clk); in ahci_dm816_phy_init()
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H A Dsata_highbank.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Calxeda Highbank AHCI SATA platform driver
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
25 #include "ahci.h"
53 /* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
88 static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port, in sgpio_bit_shift() argument
91 return 1 << (3 * pdata->port_to_sgpio[port] + shift); in sgpio_bit_shift()
94 static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state) in ecx_parse_sgpio() argument
97 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
100 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
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H A Dahci_qoriq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale QorIQ AHCI SATA platform driver
18 #include "ahci.h"
20 #define DRV_NAME "ahci-qoriq"
22 /* port register definition */
31 /* port register default value */
70 { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
71 { .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
72 { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
73 { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
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H A Dahci_ceva.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * CEVA AHCI SATA platform driver
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
16 #include "ahci.h"
64 /* Port Control Register Bit Definitions */
73 #define DRV_NAME "ahci-ceva"
78 MODULE_PARM_DESC(rx_watermark, "RxWaterMark value (0 - 0x80)");
82 /* Port Phy2Cfg Register */
124 void __iomem *mmio = hpriv->mmio; in ahci_ceva_setup()
125 struct ceva_ahci_priv *cevapriv = hpriv->plat_data; in ahci_ceva_setup()
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H A Dlibahci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * libahci.c - Common AHCI SATA low-level routines
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
27 #include <linux/dma-mapping.h>
33 #include "ahci.h"
204 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
237 * ahci_rpm_get_port - Make sure the port is powered on
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H A Dahci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ahci.h - Common AHCI SATA definitions and declarations
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
74 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
80 HOST_RESET = BIT(0), /* reset controller; self-clear */
83 HOST_AHCI_EN = BIT(31), /* AHCI enabled */
92 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
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H A Dpata_jmicron.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_jmicron.c - JMicron ATA driver for non AHCI mode. This drives the
4 * PATA port of the controller. The SATA ports are
5 * driven by AHCI in the usual configuration although
31 * jmicron_pre_reset - check for 40/80 pin
35 * Perform the PATA port setup we need.
37 * On the Jmicron 361/363 there is a single PATA port that can be mapped
44 struct ata_port *ap = link->ap; in jmicron_pre_reset()
45 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in jmicron_pre_reset()
48 int port_mask = 1<< (4 * ap->port_no); in jmicron_pre_reset()
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H A Dahci_da850.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DaVinci DA850 AHCI SATA platform driver
13 #include "ahci.h"
18 /* SATA PHY Control Register offset from AHCI base */
86 * We should have divided evenly - if not, return an invalid in ahci_da850_calculate_mpy()
102 * enable Port Multiplier support, but the drive is connected directly in ahci_da850_softreset()
108 if (pmp && ret == -EBUSY) in ahci_da850_softreset()
133 } while (retry--); in ahci_da850_hardreset()
142 * No need to override .pmp_softreset - it's only used for actual
143 * PMP-enabled ports.
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H A Dahci_xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene SoC SATA Host Controller Driver
18 #include "ahci.h"
20 #define DRV_NAME "xgene-ahci"
40 /* SATA host AHCI CSR */
91 dev_dbg(ctx->dev, "Release memory from shutdown\n"); in xgene_ahci_init_memram()
92 writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); in xgene_ahci_init_memram()
93 readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */ in xgene_ahci_init_memram()
95 if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) { in xgene_ahci_init_memram()
96 dev_err(ctx->dev, "failed to release memory from shutdown\n"); in xgene_ahci_init_memram()
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-scsi_host7 Storage Control Unit embeds up to two 4-port controllers in
34 Contact: linux-ide@vger.kernel.org
60 a) It does not use host-initiated slumber mode, but it does
61 allow device-initiated slumber
68 Contact: linux-ide@vger.kernel.org
72 as defined in the AHCI spec.
79 protocol that is being used by the driver (for eg. LED, SAF-TE,
80 SES-2, SGPIO etc).
87 Contact: linux-ide@vger.kernel.org
94 Contact: linux-ide@vger.kernel.org
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/linux/arch/arm/boot/dts/socionext/
H A Duniphier-pxs2.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/uniphier-gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "socionext,uniphier-pxs2";
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
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/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,berlin-smp";
34 next-level-cache = <&l2>;
38 clock-latency = <100000>;
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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