Lines Matching +full:ahci +full:- +full:port

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10   - Serge Semin <fancer.lancer@gmail.com>
14   implementation of the AHCI SATA controller found in Rockchip
22           - rockchip,rk3568-dwc-ahci
23           - rockchip,rk3588-dwc-ahci
25     - compatible
30       - enum:
31           - rockchip,rk3568-dwc-ahci
32           - rockchip,rk3588-dwc-ahci
33       - const: snps,dwc-ahci
35   ports-implemented:
38   power-domains:
41   sata-port@0:
42     $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
51   "^sata-port@[1-9a-e]$": false
54   - compatible
55   - reg
56   - interrupts
57   - clocks
58   - clock-names
59   - ports-implemented
62   - $ref: snps,dwc-ahci-common.yaml#
63   - if:
68               - rockchip,rk3588-dwc-ahci
73         clock-names:
75             - const: sata
76             - const: pmalive
77             - const: rxoob
78             - const: ref
79             - const: asic
80   - if:
85               - rockchip,rk3568-dwc-ahci
90         clock-names:
92             - const: sata
93             - const: pmalive
94             - const: rxoob
99   - |
100     #include <dt-bindings/clock/rockchip,rk3588-cru.h>
101     #include <dt-bindings/interrupt-controller/arm-gic.h>
102     #include <dt-bindings/ata/ahci.h>
103     #include <dt-bindings/phy/phy.h>
106       compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
111       clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
113       ports-implemented = <0x1>;
114       #address-cells = <1>;
115       #size-cells = <0>;
117       sata-port@0 {
119         hba-port-cap = <HBA_PORT_FBSCP>;
121         phy-names = "sata-phy";
122         snps,rx-ts-max = <32>;
123         snps,tx-ts-max = <32>;