xref: /linux/Documentation/devicetree/bindings/interconnect/qcom,glymur-rpmh.yaml (revision cb4eb6771c0f8fd1c52a8f6fdec7762fb087380a) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm RPMh Network-On-Chip Interconnect on Glymur and Mahua SoCs
8
9maintainers:
10  - Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
11
12description: |
13  RPMh interconnect providers support system bandwidth requirements through
14  RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
15  able to communicate with the BCM through the Resource State Coordinator (RSC)
16  associated with each execution environment. Provider nodes must point to at
17  least one RPMh device child node pertaining to their RSC and each provider
18  can map to multiple RPMh resources.
19
20  See also: include/dt-bindings/interconnect/qcom,glymur-rpmh.h
21
22properties:
23  compatible:
24    oneOf:
25      - items:
26          - enum:
27              - qcom,mahua-aggre1-noc
28          - const: qcom,glymur-aggre1-noc
29      - items:
30          - enum:
31              - qcom,mahua-aggre2-noc
32          - const: qcom,glymur-aggre2-noc
33      - items:
34          - enum:
35              - qcom,mahua-aggre3-noc
36          - const: qcom,glymur-aggre3-noc
37      - items:
38          - enum:
39              - qcom,mahua-aggre4-noc
40          - const: qcom,glymur-aggre4-noc
41      - items:
42          - enum:
43              - qcom,mahua-clk-virt
44          - const: qcom,glymur-clk-virt
45      - items:
46          - enum:
47              - qcom,mahua-cnoc-main
48          - const: qcom,glymur-cnoc-main
49      - items:
50          - enum:
51              - qcom,mahua-lpass-ag-noc
52          - const: qcom,glymur-lpass-ag-noc
53      - items:
54          - enum:
55              - qcom,mahua-lpass-lpiaon-noc
56          - const: qcom,glymur-lpass-lpiaon-noc
57      - items:
58          - enum:
59              - qcom,mahua-lpass-lpicx-noc
60          - const: qcom,glymur-lpass-lpicx-noc
61      - items:
62          - enum:
63              - qcom,mahua-mmss-noc
64          - const: qcom,glymur-mmss-noc
65      - items:
66          - enum:
67              - qcom,mahua-nsinoc
68          - const: qcom,glymur-nsinoc
69      - items:
70          - enum:
71              - qcom,mahua-nsp-noc
72          - const: qcom,glymur-nsp-noc
73      - items:
74          - enum:
75              - qcom,mahua-oobm-ss-noc
76          - const: qcom,glymur-oobm-ss-noc
77      - items:
78          - enum:
79              - qcom,mahua-pcie-east-anoc
80          - const: qcom,glymur-pcie-east-anoc
81      - items:
82          - enum:
83              - qcom,mahua-pcie-east-slv-noc
84          - const: qcom,glymur-pcie-east-slv-noc
85      - items:
86          - enum:
87              - qcom,mahua-system-noc
88          - const: qcom,glymur-system-noc
89      - enum:
90          - qcom,glymur-aggre1-noc
91          - qcom,glymur-aggre2-noc
92          - qcom,glymur-aggre3-noc
93          - qcom,glymur-aggre4-noc
94          - qcom,glymur-clk-virt
95          - qcom,glymur-cnoc-cfg
96          - qcom,glymur-cnoc-main
97          - qcom,glymur-hscnoc
98          - qcom,glymur-lpass-ag-noc
99          - qcom,glymur-lpass-lpiaon-noc
100          - qcom,glymur-lpass-lpicx-noc
101          - qcom,glymur-mc-virt
102          - qcom,glymur-mmss-noc
103          - qcom,glymur-nsinoc
104          - qcom,glymur-nsp-noc
105          - qcom,glymur-oobm-ss-noc
106          - qcom,glymur-pcie-east-anoc
107          - qcom,glymur-pcie-east-slv-noc
108          - qcom,glymur-pcie-west-anoc
109          - qcom,glymur-pcie-west-slv-noc
110          - qcom,glymur-system-noc
111          - qcom,mahua-cnoc-cfg
112          - qcom,mahua-hscnoc
113          - qcom,mahua-mc-virt
114          - qcom,mahua-pcie-west-anoc
115          - qcom,mahua-pcie-west-slv-noc
116
117  reg:
118    maxItems: 1
119
120  clocks:
121    minItems: 1
122    maxItems: 4
123
124required:
125  - compatible
126
127allOf:
128  - $ref: qcom,rpmh-common.yaml#
129  - if:
130      properties:
131        compatible:
132          contains:
133            enum:
134              - qcom,glymur-clk-virt
135              - qcom,glymur-mc-virt
136              - qcom,mahua-mc-virt
137    then:
138      properties:
139        reg: false
140    else:
141      required:
142        - reg
143
144  - if:
145      properties:
146        compatible:
147          contains:
148            enum:
149              - qcom,glymur-pcie-west-anoc
150    then:
151      properties:
152        clocks:
153          items:
154            - description: aggre PCIE_3A WEST AXI clock
155            - description: aggre PCIE_3B WEST AXI clock
156            - description: aggre PCIE_4 WEST AXI clock
157            - description: aggre PCIE_6 WEST AXI clock
158
159  - if:
160      properties:
161        compatible:
162          contains:
163            enum:
164              - qcom,mahua-pcie-west-anoc
165    then:
166      properties:
167        clocks:
168          items:
169            - description: aggre PCIE_3B WEST AXI clock
170            - description: aggre PCIE_4 WEST AXI clock
171            - description: aggre PCIE_6 WEST AXI clock
172
173  - if:
174      properties:
175        compatible:
176          contains:
177            enum:
178              - qcom,glymur-pcie-east-anoc
179    then:
180      properties:
181        clocks:
182          items:
183            - description: aggre PCIE_5 EAST AXI clock
184
185  - if:
186      properties:
187        compatible:
188          contains:
189            enum:
190              - qcom,glymur-aggre2-noc
191    then:
192      properties:
193        clocks:
194          items:
195            - description: aggre USB3 TERT AXI clock
196            - description: aggre USB4_2 AXI clock
197            - description: aggre UFS PHY AXI clock
198
199  - if:
200      properties:
201        compatible:
202          contains:
203            enum:
204              - qcom,glymur-aggre4-noc
205    then:
206      properties:
207        clocks:
208          items:
209            - description: aggre USB3 PRIM AXI clock
210            - description: aggre USB3 SEC AXI clock
211            - description: aggre USB4_0 AXI clock
212            - description: aggre USB4_1 AXI clock
213
214  - if:
215      properties:
216        compatible:
217          contains:
218            enum:
219              - qcom,glymur-aggre2-noc
220              - qcom,glymur-aggre4-noc
221              - qcom,glymur-pcie-east-anoc
222              - qcom,glymur-pcie-west-anoc
223              - qcom,mahua-pcie-west-anoc
224    then:
225      required:
226        - clocks
227    else:
228      properties:
229        clocks: false
230
231unevaluatedProperties: false
232
233examples:
234  - |
235    #include <dt-bindings/clock/qcom,glymur-gcc.h>
236    clk_virt: interconnect-0 {
237      compatible = "qcom,glymur-clk-virt";
238      #interconnect-cells = <2>;
239      qcom,bcm-voters = <&apps_bcm_voter>;
240    };
241
242    aggre1_noc: interconnect@16e0000 {
243      compatible = "qcom,glymur-aggre1-noc";
244      reg = <0x016e0000 0x14400>;
245      #interconnect-cells = <2>;
246      qcom,bcm-voters = <&apps_bcm_voter>;
247    };
248
249    aggre4_noc: interconnect@1740000 {
250      compatible = "qcom,glymur-aggre4-noc";
251      reg = <0x01740000 0x14400>;
252      #interconnect-cells = <2>;
253      qcom,bcm-voters = <&apps_bcm_voter>;
254      clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
255               <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
256               <&gcc GCC_AGGRE_USB4_0_AXI_CLK>,
257               <&gcc GCC_AGGRE_USB4_1_AXI_CLK>;
258    };
259