| /linux/arch/parisc/include/asm/ |
| H A D | elf.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */
29 #define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */
30 #define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */
60 #define R_PARISC_DIR32 1 /* Direct 32-bit reference. */
61 #define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */
62 #define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */
63 #define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */
64 #define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */
65 #define R_PARISC_PCREL32 9 /* 32-bit rel. address. */
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| /linux/drivers/ras/amd/atl/ |
| H A D | reg_fields.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * AMD Address Translation Library
28 * Rev Fieldname Bits
46 * Rev Fieldname Bits
69 * Rev Fieldname Bits
71 * D18F0x114 [DRAM Limit Address]
76 * D18F7xE08 [DRAM Address Control]
79 * D18F7x208 [DRAM Address Control]
94 * Rev Fieldname Bits
119 * Rev Fieldname Bits
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| /linux/Documentation/userspace-api/media/rc/ |
| H A D | rc-protos.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
10 protocols can encode e.g. an address (which device should respond) and a
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
32 This IR protocol uses manchester encoding to encode 14 bits. There is a
38 .. flat-table:: rc5 bits scancode mapping
41 * - rc-5 bit
43 - scancode bit
45 - description
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap3-echo.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
14 compatible = "amazon,omap3-echo", "ti,omap3630", "ti,omap3";
18 cpu0-supply = <&vdd1_reg>;
28 compatible = "regulator-fixed";
29 regulator-name = "vcc5v";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
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| /linux/drivers/acpi/pmic/ |
| H A D | tps68470_pmic.c | 1 // SPDX-License-Identifier: GPL-2.0
19 u32 address; /* operation region address */ member
38 .address = 0x00,
44 .address = 0x04,
50 .address = 0x08,
56 .address = 0x0C,
62 .address = 0x10,
68 .address = 0x14,
78 .address = 0x00,
84 .address = 0x04,
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | psp_gfx_if.h | 46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
57 /*-----------------------------------------------------------------------------
64 * SRBM-to-PSP mailbox registers (total 8 registers).
73 … volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
74 …volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) …
116 /* PSP boot config sub-commands */
133 …uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary…
134 …uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binar…
136 …uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (m…
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| /linux/tools/include/linux/ |
| H A D | find.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 * find_next_bit - find the next set bit in a memory region
25 * @addr: The address to base the search on
26 * @size: The bitmap size in bits
30 * If no bits are set, returns @size.
42 val = *addr & GENMASK(size - 1, offset); in find_next_bit()
52 * find_next_and_bit - find the next set bit in both memory regions
53 * @addr1: The first address to base the search on
54 * @addr2: The second address to base the search on
55 * @size: The bitmap size in bits
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| /linux/include/linux/iio/imu/ |
| H A D | adis.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
28 * struct adis_timeouts - ADIS chip variant timeouts
29 * @reset_ms - Wait time after rst pin goes inactive
30 * @sw_reset_ms - Wait time after sw reset command
31 * @self_test_ms - Wait time after self test command
40 * struct adis_data - ADIS chip variant specific data
44 * @glob_cmd_reg: Register address of the GLOB_CMD register
45 * @msc_ctrl_reg: Register address of the MSC_CTRL register
46 * @diag_stat_reg: Register address of the DIAG_STAT register
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| /linux/drivers/acpi/acpica/ |
| H A D | hwregs.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: hwregs - Read/write access functions for the various ACPI
19 acpi_hw_get_access_bit_width(u64 address,
39 * PARAMETERS: address - GAS register address
40 * reg - GAS register structure
41 * max_bit_width - Max bit_width supported (32 or 64)
50 acpi_hw_get_access_bit_width(u64 address, in acpi_hw_get_access_bit_width() argument
66 * Note: This algorithm assumes that the "Address" fields should always in acpi_hw_get_access_bit_width()
69 if (!reg->bit_offset && reg->bit_width && in acpi_hw_get_access_bit_width()
70 ACPI_IS_POWER_OF_TWO(reg->bit_width) && in acpi_hw_get_access_bit_width()
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| /linux/arch/mips/include/asm/octeon/ |
| H A D | cvmx.h | 7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
56 #include <asm/octeon/cvmx-asm.h>
57 #include <asm/octeon/cvmx-packet.h>
58 #include <asm/octeon/cvmx-sysinfo.h>
60 #include <asm/octeon/cvmx-ciu-defs.h>
61 #include <asm/octeon/cvmx-ciu3-defs.h>
62 #include <asm/octeon/cvmx-gpio-defs.h>
63 #include <asm/octeon/cvmx-iob-defs.h>
[all …]
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| /linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/ |
| H A D | pipeline.json | 51 …number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it b…
54 …number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it b…
57 …number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it b…
60 …number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it b…
75 …on": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1.",
78 …ion": "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1."
81 …on": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1.",
84 …ion": "This event counts requests in L1D cache pipeline#0 that its pfe bit of tagged address is 1."
87 …on": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1.",
90 …ion": "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1."
[all …]
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| /linux/Documentation/networking/ |
| H A D | ila.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 Identifier-locator addressing (ILA) is a technique used with IPv6 that
13 address expresses the immutable identity of the node, and another part
14 indicates the location of the node which can be dynamic. Identifier-locator
19 encapsulation. This is accomplished by performing network address
27 The ILA protocol is described in Internet-Draft draft-herbert-intarea-ila.
33 - Identifier
35 independent of its location. ILA identifiers are sixty-four
38 - Locator
41 locators are sixty-four bit prefixes.
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| /linux/arch/x86/include/asm/uv/ |
| H A D | uv_hub.h | 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
33 * M - The low M bits of a physical address represent the offset
38 * N - Number of bits in the node portion of a socket physical
39 * address.
41 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
44 * right shift the NASID by 1 to exclude the always-zero bit.
45 * NASIDs contain up to 15 bits.
47 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
50 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
53 * GPA - (global physical address) a socket physical address converted
[all …]
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| /linux/include/linux/dma/ |
| H A D | qcom_bam_dma.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
15 * @cmd_and_addr - upper 8 bits command and lower 24 bits register address.
16 * @data - For write command: content to be written into peripheral register.
17 * For read command: lower 32 bits of destination address.
18 * @mask - For write command: register write mask.
19 * For read command on BAM v1.6.0+: upper 4 bits of destination address.
21 * Setting to 0 ensures 32-bit addressing compatibility.
22 * @reserved - for future usage.
41 * prep_bam_ce_le32 - Wrapper function to prepare a single BAM command
[all …]
|
| /linux/lib/ |
| H A D | genalloc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * kmalloc/kfree interface. Uses for this includes on-device special
21 * On architectures that don't have NMI-safe cmpxchg implementation,
26 * Copyright 2005 (C) Jes Sorensen <jes@trained-monkey.org>
42 return chunk->end_addr - chunk->start_addr + 1; in chunk_size()
52 return -EBUSY; in set_bits_ll()
66 return -EBUSY; in clear_bits_ll()
74 * bitmap_set_ll - set the specified number of bits at the specified position
77 * @nr: number of bits to set
79 * Set @nr bits start from @start in @map lock-lessly. Several users
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| /linux/Documentation/trace/coresight/ |
| H A D | coresight-etm4x-reference.rst | 11 ---------------------------
20 ----
25 Bit select trace features. See ‘mode’ section below. Bits
32 bitfield up to 32 bits setting trace features.
37 ----
47 ----
52 - > 0 : Programs up the hardware with the current values held in the driver
55 - = 0 : disable trace hardware.
60 ----
72 ----
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| /linux/Documentation/devicetree/bindings/leds/backlight/ |
| H A D | lp855x-backlight.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/lp855x-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Artur Weber <aweber.kernel@gmail.com>
15 - ti,lp8550
16 - ti,lp8551
17 - ti,lp8552
18 - ti,lp8553
19 - ti,lp8555
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| /linux/drivers/net/fjes/ |
| H A D | fjes_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
25 #define XSCT_SHSTSAL 0x0028 /* Share status address Low */
26 #define XSCT_SHSTSAH 0x002C /* Share status address High */
29 #define XSCT_REQBAL 0x0038 /* Request Buffer Address Low */
30 #define XSCT_REQBAH 0x003C /* Request Buffer Address High */
33 #define XSCT_RESPBAL 0x0048 /* Response Buffer Address Low */
34 #define XSCT_RESPBAH 0x004C /* Response Buffer Address High */
49 } bits; member
57 } bits; member
67 } bits; member
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| /linux/drivers/comedi/drivers/ |
| H A D | plx9080.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
27 * @pci_start_addr: PCI Bus address for transfer (DMAPADR).
28 * @local_start_addr: Local Bus address for transfer (DMALADR).
30 * @next: Address of next descriptor + flags (DMADPR).
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
38 * of @next contain flags describing the address space of the next
53 /* Local Address Space 0 Range Register */
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| /linux/drivers/net/fddi/ |
| H A D | defza.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* FDDI network adapter driver for DEC FDDIcontroller 700/700-C devices.
25 #define FZA_REG_BASE 0x100000 /* register base address */
33 /* Reset register constants. Bits 1:0 are r/w, others are fixed at 0. */
36 #define FZA_RESET_CLR 0x0000 /* run self-test and return to work */
38 /* Interrupt event register constants. All bits are r/w1c. */
43 #define FZA_EVENT_NXM_ERR 0x0080 /* non-existent memory access error;
45 * unsupported partial-word accesses
55 /* Status register constants. All bits are r/o. */
56 #define FZA_STATUS_DLU_SHIFT 0xc /* down line upgrade status bits */
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| /linux/include/linux/mtd/ |
| H A D | pfow.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 /* Address of symbol "P" */
13 /* Address of symbol "F" */
15 /* Address of symbol "O" */
17 /* Address of symbol "W" */
22 /* Address in PFOW where prog buffer can be found */
26 /* Address command code register */
30 /* command address register lower address bits */
32 /* command address register upper address bits */
34 /* number of bytes to be proggrammed lower address bits */
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| /linux/arch/arm/boot/dts/aspeed/ |
| H A D | aspeed-bmc-lenovo-hr630.dts | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2019-present Lenovo
8 /dts-v1/;
10 #include "aspeed-g5.dtsi"
11 #include <dt-bindings/gpio/aspeed-gpio.h>
15 compatible = "lenovo,hr630-bmc", "aspeed,ast2500";
29 stdout-path = &uart5;
38 reserved-memory {
39 #address-cells = <1>;
40 #size-cells = <1>;
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| /linux/Documentation/devicetree/bindings/dpll/ |
| H A D | microchip,zl30731.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ivan Vecera <ivecera@redhat.com>
15 single-ended inputs and 10 differential or 20 single-ended outputs.
24 - enum:
25 - microchip,zl30731
26 - microchip,zl30732
27 - microchip,zl30733
28 - microchip,zl30734
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| /linux/Documentation/virt/kvm/devices/ |
| H A D | arm-vgic-v3.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
24 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
25 Base address in the guest physical address space of the GICv3 distributor
27 This address needs to be 64K aligned and the region covers 64 KByte.
29 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
30 Base address in the guest physical address space of the GICv3
34 This address needs to be 64K aligned.
36 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
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| /linux/drivers/net/ethernet/xilinx/ |
| H A D | xilinx_axienet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
92 #define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */
111 #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
131 #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
141 #define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */
146 #define XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
154 #define XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */
155 #define XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */
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|