Lines Matching +full:address +full:- +full:bits

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * AMD Address Translation Library
28  *	Rev	Fieldname	Bits
46  *	Rev	Fieldname	Bits
69  *	Rev	Fieldname	Bits
71  *	D18F0x114 [DRAM Limit Address]
76  *	D18F7xE08 [DRAM Address Control]
79  *	D18F7x208 [DRAM Address Control]
94  *	Rev	Fieldname	Bits
119  *	Rev	Fieldname	Bits
132  * DRAM Address Range Valid
137  *	Rev	Fieldname	Bits
139  *	D18F0x110 [DRAM Base Address]
144  *	D18F7xE08 [DRAM Address Control]
147  *	D18F7x208 [DRAM Address Control]
153  * DRAM Base Address
158  *	Rev	Fieldname	Bits
160  *	D18F0x110 [DRAM Base Address]
165  *	D18F7xE00 [DRAM Base Address]
168  *	D18F7x200 [DRAM Base Address]
180  *	Rev	Fieldname	Bits
194  * DRAM Limit Address
199  *	Rev	Fieldname	Bits
201  *	D18F0x114 [DRAM Limit Address]
206  *	D18F7xE04 [DRAM Limit Address]
209  *	D18F7x204 [DRAM Limit Address]
221  *	Rev	Fieldname	Bits
234  *	D18F7xE08 [DRAM Address Control]
239  *	D18F7x208 [DRAM Address Control]
256  * High Address Offset
261  *	Rev	Fieldname	Bits
276 /* Follow reference code by including reserved bits for simplicity. */
280  * High Address Offset Enable
285  *	Rev	Fieldname	Bits
299  * Interleave Address Select
304  *	Rev	Fieldname	Bits
306  *	D18F0x110 [DRAM Base Address]
311  *	D18F7xE0C [DRAM Address Interleave]
314  *	D18F7x20C [DRAM Address Interleave]
327  *	Rev	Fieldname	Bits
329  *	D18F0x110 [DRAM Base Address]
334  *	D18F7xE0C [DRAM Address Interleave]
337  *	D18F7x20C [DRAM Address Interleave]
352  *	Rev	Fieldname	Bits
354  *	D18F0x114 [DRAM Limit Address]
357  *	D18F0x110 [DRAM Base Address]
361  *	D18F7xE0C [DRAM Address Interleave]
364  *	D18F7x20C [DRAM Address Interleave]
378  *	Rev	Fieldname	Bits
380  *	D18F0x114 [DRAM Limit Address]
383  *	D18F0x110 [DRAM Base Address]
387  *	D18F7xE0C [DRAM Address Interleave]
390  *	D18F7x20C [DRAM Address Interleave]
402  *	Rev	Fieldname	Bits
404  *	D18F0x110 [DRAM Base Address]
409  *	D18F7xE08 [DRAM Address Control]
412  *	D18F7x208 [DRAM Address Control]
418  * Log2 Address 64K Space 0
423  *	Rev	Fieldname		Bits
427  *	D18F2x90 [Non-power-of-2 channel Configuration Register for COH_ST DRAM Address Maps]
442  *	Rev	Fieldname	Bits
460  *	Rev	Fieldname	Bits
478  *	Rev	Fieldname	Bits
501  *	Rev	Fieldname	Bits
523  *	Rev	Fieldname	Bits
529  *	D18F7xE08 [DRAM Address Control]
532  *	D18F7x208 [DRAM Address Control]
543  *	Rev	Fieldname	Bits
549  *	D18F7xE08 [DRAM Address Control]
552  *	D18F7x208 [DRAM Address Control]
564  *	Rev	Fieldname	Bits
589  *		Rev	Fieldname	Bits