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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Damlogic,meson-saradc.txt22 - "adc_sel" for the ADC (sampling) clock mux
47 clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
H A Damlogic,meson-saradc.yaml48 - const: adc_sel
137 clock-names = "clkin", "core", "adc_clk", "adc_sel";
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a.c977 u32 adc_sel[2] = {0x12d0, 0x32d0}; in rtw8852a_bw_setting() local
988 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); in rtw8852a_bw_setting()
993 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); in rtw8852a_bw_setting()
998 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); in rtw8852a_bw_setting()
1003 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); in rtw8852a_bw_setting()
1008 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); in rtw8852a_bw_setting()
H A Drtw8852b_common.c808 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; in rtw8852b_bw_setting() local
813 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); in rtw8852b_bw_setting()
817 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); in rtw8852b_bw_setting()
821 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); in rtw8852b_bw_setting()
825 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); in rtw8852b_bw_setting()
829 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); in rtw8852b_bw_setting()
H A Drtw8852c.c1101 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; in rtw8852c_bw_setting() local
1106 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); in rtw8852c_bw_setting()
1110 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); in rtw8852c_bw_setting()
1117 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); in rtw8852c_bw_setting()
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-a1.dtsi355 "adc_clk", "adc_sel";
H A Dmeson-gxbb.dtsi793 clock-names = "clkin", "core", "adc_clk", "adc_sel";
H A Dmeson-gxl.dtsi863 clock-names = "clkin", "core", "adc_clk", "adc_sel";
H A Dmeson-axg.dtsi1754 clock-names = "clkin", "core", "adc_clk", "adc_sel";
H A Dmeson-g12-common.dtsi2125 clock-names = "clkin", "core", "adc_clk", "adc_sel";