| /freebsd/sys/dev/bhnd/bhndb/ |
| H A D | bhndb_pcireg.h | 132 #define BHNDB_PCI_V0_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplan…
134 #define BHNDB_PCI_V0_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */
136 #define BHNDB_PCI_V0_BAR0_PCIREG_OFFSET 0x1800 /* bar0 + 6K accesses pci core registers (not includ…
138 #define BHNDB_PCI_V0_BAR0_PCISB_OFFSET 0x1E00 /* bar0 + 7.5K accesses pci core's SSB CFG register b…
147 #define BHNDB_PCI_V1_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplan…
149 #define BHNDB_PCI_V1_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */
151 #define BHNDB_PCI_V1_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */
153 #define BHNDB_PCI_V1_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */
162 #define BHNDB_PCI_V2_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplan…
164 #define BHNDB_PCI_V2_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */
[all …]
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| /freebsd/share/man/man9/ |
| H A D | kasan.9 | 52 memory accesses in the kernel.
63 accesses.
73 Memory accesses through the kernel map are sanitized, but accesses via the
83 before most memory accesses in the generated code.
109 Accesses to the buffer are intercepted by the
168 Accesses to kernel memory outside of the kernel map are ignored by the
175 For example, on amd64 and arm64, accesses to page table pages are not tracked.
177 Some kernel memory allocators explicitly permit accesses after an object has
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| H A D | atomic.9 | 153 By default, a thread's accesses to different memory locations might not be
156 that is, the order in which the accesses appear in the source code.
158 reorder the thread's accesses.
159 However, both ensure that their reordering of the accesses is not visible to
170 on a thread's accesses, a programmer can use atomic operations with
180 accesses to other memory locations.
240 constrain the reordering of accesses.
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| /freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/ |
| H A D | frontend.json | 74 "EventName": "ICACHE.ACCESSES",
77 … accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count …
89 … accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count…
101 … accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count…
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| /freebsd/sys/contrib/openzfs/man/man1/ |
| H A D | arcstat.1 | 140 Total ARC accesses per second
151 Demand accesses per second
153 Demand data accesses per second
155 Demand metadata accesses per second
161 Metadata accesses per second
163 Prefetch accesses per second
165 Prefetch data accesses per second
167 Prefetch metadata accesses per second
175 Total L2ARC accesses per second
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| /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/ |
| H A D | recommended.json | 12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
90 "BriefDescription": "L3 Accesses",
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| /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/ |
| H A D | recommended.json | 12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
90 "BriefDescription": "L3 Accesses",
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | LoopAccessAnalysis.h | 60 /// Checks memory dependences among accesses to the same underlying
70 /// on the program order of memory accesses to determine their safety.
71 /// At the moment we will only deem accesses as safe for:
92 /// * Zero distances and all accesses have the same size.
98 /// Set of potential dependent memory accesses.
199 /// Check whether the dependencies between the accesses are safe.
261 /// Returns an empty ArrayRef if there are no accesses for the location.
263 auto I = Accesses.find({Ptr, IsWrite}); in getOrderForAccess()
264 if (I != Accesses.end()) in getOrderForAccess()
292 DenseMap<MemAccessInfo, std::vector<unsigned> > Accesses; variable
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/ |
| H A D | recommended.json | 12 "BriefDescription": "All L1 Data Cache Accesses",
17 "BriefDescription": "All L2 Cache Accesses",
24 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
30 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
35 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
90 "BriefDescription": "L3 Cache Accesses",
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| /freebsd/lib/libpmc/pmu-events/arch/x86/elkhartlake/ |
| H A D | frontend.json | 74 "EventName": "ICACHE.ACCESSES",
77 … accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count …
89 … accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count…
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | LoopAccessAnalysis.cpp | 71 #define DEBUG_TYPE "loop-accesses"
112 /// accesses in code like the following.
487 // the accesses are safe. in groupChecks()
499 // accesses to the same underlying object. This cannot happen unless in groupChecks()
527 // and add them to the overall solution. We use the order in which accesses in groupChecks()
541 // Because DepCands is constructed by visiting accesses in the order in in groupChecks()
638 OS.indent(Depth) << "Grouped accesses:\n"; in print()
651 /// Analyses memory accesses in a loop.
675 Accesses[MemAccessInfo(Ptr, false)].insert(AccessTy); in addLoad()
684 Accesses[MemAccessInfo(Ptr, true)].insert(AccessTy); in addStore()
[all …]
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| H A D | MemorySSA.cpp | 475 // We do have accesses that claim they're optimized, but could be optimized in checkClobberSanity()
1009 /// A MemorySSAWalker that does AA walks to disambiguate accesses. It no
1103 AccessList *Accesses = It->second.get(); in renameSuccessorPhis() local
1104 auto *Phi = cast<MemoryPhi>(&Accesses->front()); in renameSuccessorPhis()
1127 AccessList *Accesses = It->second.get(); in renameBlock() local
1128 for (MemoryAccess &L : *Accesses) { in renameBlock()
1144 /// We walk the dominator tree in preorder, renaming accesses, and then filling
1149 assert(Root && "Trying to rename accesses in an unreachable block"); in renamePass()
1193 /// This handles unreachable block accesses by deleting phi nodes in
1211 AccessList *Accesses = It->second.get(); in markUnreachableAsLiveOnEntry() local
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/arm64/hisilicon/hip08/ |
| H A D | uncore-l3c.json | 5 "BriefDescription": "Total read accesses",
6 "PublicDescription": "Total read accesses",
12 "BriefDescription": "Total write accesses",
13 "PublicDescription": "Total write accesses",
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| /freebsd/sys/contrib/device-tree/Bindings/ |
| H A D | common-properties.txt | 13 - big-endian: Boolean; force big endian register accesses
16 - little-endian: Boolean; force little endian register accesses
19 - native-endian: Boolean; always use register accesses matched to the
30 default to LE for their MMIO accesses.
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| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | cache.json | 159 …"PublicDescription": "Level 2 TLB level-2 walk cache access.This event counts accesses to the leve…
162 …"BriefDescription": "Level 2 TLB level-2 walk cache access.This event counts accesses to the level…
171 …cess to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache,…
174 …cess to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache,…
177 …fill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache,…
180 …fill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache,…
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | baikal,bt1-l2-ctl.yaml | 29 description: Cycles of latency for Way-select RAM accesses
36 description: Cycles of latency for Tag RAM accesses
43 description: Cycles of latency for Data RAM accesses
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| /freebsd/sys/contrib/device-tree/Bindings/cache/ |
| H A D | baikal,bt1-l2-ctl.yaml | 29 description: Cycles of latency for Way-select RAM accesses
36 description: Cycles of latency for Tag RAM accesses
43 description: Cycles of latency for Data RAM accesses
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | gpio-control-nand.txt | 10 resource describes the data bus connected to the NAND flash and all accesses
23 location used to guard against bus reordering with regards to accesses to
26 read to ensure that the GPIO accesses have completed.
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| /freebsd/lib/libpmc/pmu-events/arch/x86/goldmont/ |
| H A D | frontend.json | 47 "EventName": "ICACHE.ACCESSES",
48 …e line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight lin…
58 …t). The event strives to count on a cache line basis, so that multiple accesses which hit in a si…
68 …s). The event strives to count on a cache line basis, so that multiple accesses which miss in a s…
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| /freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/ |
| H A D | frontend.json | 55 "EventName": "ICACHE.ACCESSES",
58 …e line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight lin…
70 …t). The event strives to count on a cache line basis, so that multiple accesses which hit in a si…
82 …s). The event strives to count on a cache line basis, so that multiple accesses which miss in a s…
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| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| H A D | cache.json | 11 …walk access which causes data to be read from outside the L1, including accesses which do not allo…
23 … 0 Macro-op cache access. This event counts any instruction fetch which accesses the L1 instructio…
47 …"PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB…
52 …"PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TL…
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| /freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/ |
| H A D | other.json | 145 …less in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controll…
189 …less in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controll…
200 …nless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controll…
288 …less in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controll…
299 …nless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controll…
365 …less in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controll…
420 …"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hav…
453 …less in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controll…
464 …nless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controll…
475 … whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controll…
[all …]
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| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | cache.json | 156 …he IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache,…
159 …he IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache,…
162 …he IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache,…
165 …he IPA cache. If a single translation table walk needs to make multiple accesses to the IPA cache,…
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| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/ |
| H A D | cache.json | 165 …"PublicDescription": "Level 2 TLB level-2 walk cache access. This event counts accesses to the lev…
168 …"BriefDescription": "Level 2 TLB level-2 walk cache access. This event counts accesses to the leve…
177 …cess to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache,…
180 …cess to the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache,…
183 …fill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache,…
186 …fill of the IPA cache. +//0 If a single pagewalk needs to make multiple accesses to the IPA cache,…
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| /freebsd/lib/libpmc/ |
| H A D | pmc.amd.3 | 174 Count data cache accesses including microcode scratch pad accesses.
209 .It Li k8-dc-dcache-accesses-by-locks Op Li ,mask= Ns Ar qualifier
211 Count data cache accesses by lock instructions.
221 .It Li accesses
222 Count data cache accesses by lock instructions.
227 The default is to count all accesses.
255 Count microarchitectural early cancels of data cache accesses.
258 Count microarchitectural late cancels of data cache accesses.
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