| /linux/Documentation/driver-api/gpio/ |
| H A D | drivers-on-gpio.rst | 2 Subsystem drivers using GPIO
5 Note that standard kernel drivers exist for common GPIO tasks and will provide
6 the right in-kernel and userspace APIs/ABIs for the job, and that these
10 - leds-gpio: drivers/leds/leds-gpio.c will handle LEDs connected to GPIO
13 - ledtrig-gpio: drivers/leds/trigger/ledtrig-gpio.c will provide a LED trigger,
14 i.e. a LED will turn on/off in response to a GPIO line going high or low
15 (and that LED may in turn use the leds-gpio as per above).
17 - gpio-keys: drivers/input/keyboard/gpio_keys.c is used when your GPIO line
18 can generate interrupts in response to a key press. Also supports debounce.
20 - gpio-keys-polled: drivers/input/keyboard/gpio_keys_polled.c is used when your
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| H A D | intro.rst | 6 GPIO Interfaces
10 GPIOs in drivers, and how to write a driver for a device that provides GPIOs
14 What is a GPIO?
17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
19 to Linux developers working with embedded and custom hardware. Each GPIO
20 represents a bit connected to a particular pin, or "ball" on Ball Grid Array
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
29 often have a few such pins to help with pin scarcity on SOCs; and there are
30 also "GPIO Expander" chips that connect using the I2C or SPI serial buses.
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| H A D | consumer.rst | 2 GPIO Descriptor Consumer Interface
5 This document describes the consumer interface of the GPIO framework.
11 Drivers that can't work without standard GPIO calls should have Kconfig entries
12 that depend on GPIOLIB or select GPIOLIB. The functions that allow a driver to
15 #include <linux/gpio/consumer.h>
21 - Simple compile coverage with e.g. COMPILE_TEST - it does not matter that
25 - Truly optional GPIOLIB support - where the driver does not really make use
26 of the GPIOs on certain compile-time configurations for certain systems, but
27 will use it under other compile-time configurations. In this case the
31 ``[devm_]gpiod_get_optional()`` is a *bad idea*, and will result in weird
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| /linux/drivers/gpio/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # GPIO infrastructure and drivers
10 bool "GPIO Support"
12 This enables GPIO support through the generic GPIO library.
14 one or more of the GPIO drivers below.
26 using a stack allocated buffer to a dynamically allocated buffer.
50 this symbol, but new drivers should use the generic gpio-regmap
54 bool "Debug GPIO calls"
57 Say Y here to add some extra checks and diagnostics to GPIO calls.
60 non-sleeping contexts. They can make bitbanged serial protocols
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| H A D | gpiolib-devres.c | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * devres.c - managed gpio resources
15 #include <linux/gpio/consumer.h>
33 * devm_gpiod_get - Resource-managed gpiod_get()
34 * @dev: GPIO consumer
35 * @con_id: function within the GPIO consumer
36 * @flags: optional GPIO initialization flags
38 * Managed gpiod_get(). GPIO descriptors returned from this function are
43 * The GPIO descriptor corresponding to the function @con_id of device
44 * dev, %-ENOENT if no GPIO has been assigned to the requested function, or
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| H A D | gpio-pcf857x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders
9 #include <linux/gpio/consumer.h>
10 #include <linux/gpio/driver.h>
60 * write register. Writing a "one" bit (to match the reset state) lets
61 * that pin be used as an input; it's not an open-drain model, but acts
62 * a bit like one. This is described as "quasi-bidirectional"; read the
65 * Many other I2C GPIO expander chips (like the pca953x models) have
82 /*-------------------------------------------------------------------------*/
84 /* Talk to 8-bit I/O expander */
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| /linux/Documentation/admin-guide/gpio/ |
| H A D | gpio-aggregator.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
3 GPIO Aggregator
6 The GPIO Aggregator provides a mechanism to aggregate GPIOs, and expose them as
7 a new gpio_chip. This supports the following use cases.
11 -----------------------------
13 GPIO controllers are exported to userspace using /dev/gpiochip* character
15 system permissions, on an all-or-nothing basis: either a GPIO controller is
16 accessible for a user, or it is not.
18 The GPIO Aggregator provides access control for a set of one or more GPIOs, by
19 aggregating them into a new gpio_chip, which can be assigned to a group or user
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| H A D | gpio-sim.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Configfs GPIO Simulator
6 The configfs GPIO Simulator (gpio-sim) provides a way to create simulated GPIO
8 using the standard GPIO character device interface as well as manipulated
12 ------------------------
14 The gpio-sim module registers a configfs subsystem called ``'gpio-sim'``. For
17 The user can create a hierarchy of configfs groups and items as well as modify
21 **Group:** ``/config/gpio-sim``
23 This is the top directory of the gpio-sim configfs tree.
25 **Group:** ``/config/gpio-sim/gpio-device``
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| /linux/Documentation/userspace-api/gpio/ |
| H A D | sysfs.rst | 1 GPIO Sysfs Interface for Userspace
6 been moved to Documentation/ABI/obsolete/sysfs-gpio.
16 ----------------------
18 configure a sysfs user interface to GPIOs. This is different from the
19 debugfs interface, since it provides control over GPIO direction and
20 value instead of just showing a gpio state summary. Plus, it could be
24 know for example that GPIO #23 controls the write protect line used to
26 may need to temporarily remove that protection, first importing a GPIO,
27 then changing its output state, then updating the code before re-enabling
28 the write protection. In normal use, GPIO #23 would never be touched,
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| H A D | chardev_v1.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 GPIO Character Device Userspace API (v1)
12 in the future. The v2 API is a functional superset of the v1 API so any
13 v1 call can be directly translated to a v2 equivalent.
20 The API is based around three major objects, the :ref:`gpio-v1-chip`, the
21 :ref:`gpio-v1-line-handle`, and the :ref:`gpio-v1-line-event`.
24 monitor a line for edge events, not the edge events themselves.
26 .. _gpio-v1-chip:
31 The Chip represents a single GPIO chip and is exposed to userspace using device
34 Each chip supports a number of GPIO lines,
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| /linux/Documentation/driver-api/ |
| H A D | pin-control.rst | 9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
29 there may be several such number spaces in a system. This pin space may
30 be sparse - i.e. there may be gaps in the space with numbers where no
33 When a PIN CONTROLLER is instantiated, it will register a descriptor to the
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | pinctrl-st.txt | 3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
16 First type is via irqmux, single interrupt is used by multiple gpio banks. This
18 a single pincontroller.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
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| H A D | st,stm32-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: STM32 GPIO and Pin Mux/Config controller
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
14 STMicroelectronics's STM32 MCUs integrate a GPIO and Pin mux/config hardware
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
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| H A D | pinctrl-vt8500.txt | 1 VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
3 These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
4 either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).
7 - compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
8 "wm8750-pinctrl" or "wm,wm8850-pinctrl"
9 - reg: Should contain the physical address of the module's registers.
10 - interrupt-controller: Marks the device node as an interrupt controller.
11 - #interrupt-cells: Should be two.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells : Should be two. The first cell is the pin number and the
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| H A D | renesas,rza1-ports.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 combined Pin and GPIO controller
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
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| H A D | nuvoton,wpcm450-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton WPCM450 pin control and GPIO
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
14 const: nuvoton,wpcm450-pinctrl
19 '#address-cells':
22 '#size-cells':
27 # 1. a GPIO controller node for each GPIO bank
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| /linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | gpio-restart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
13 Drive a GPIO line that can be used to restart the system from a restart handler.
16 request the given gpio line and install a restart handler. If the optional properties
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
20 When the system is restarted, the restart handler will be invoked in priority order. The GPIO
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | cirrus,cs35l45.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
11 - Richard Fitzgerald <rf@opensource.cirrus.com>
14 CS35L45 is a Boosted Mono Class D Amplifier with DSP
18 - $ref: dai-common.yaml#
23 - cirrus,cs35l45
31 '#sound-dai-cells':
34 reset-gpios:
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| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | xlnx,gpio-xilinx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI GPIO controller
10 - Neeli Srinivas <srinivas.neeli@amd.com>
13 The AXI GPIO design provides a general purpose input/output interface
14 to an AXI4-Lite interface. The AXI GPIO can be configured as either
15 a single or a dual-channel device. The width of each channel is
17 generate an interrupt when a transition on any of their inputs occurs.
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| H A D | snps,dw-apb-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB GPIO controller
10 Synopsys DesignWare GPIO controllers have a configurable number of ports,
12 GPIO-controller properties as described in this bindings file.
15 - Hoan Tran <hoan@os.amperecomputing.com>
16 - Serge Semin <fancer.lancer@gmail.com>
20 pattern: "^gpio@[0-9a-f]+$"
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| H A D | nxp,pcf8575.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nxp,pcf8575.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCF857x-compatible I/O expanders
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
14 driven high by a pull-up current source or driven low to ground. This
15 combines the direction and output level into a single bit per line, which
16 can't be read back. We can't actually know at initialization time whether a
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| /linux/Documentation/i2c/muxes/ |
| H A D | i2c-mux-gpio.rst | 2 Kernel driver i2c-mux-gpio
8 -----------
10 i2c-mux-gpio is an i2c mux driver providing access to I2C bus segments
11 from a master I2C bus and a hardware MUX controlled through GPIO pins.
15 ---------- ---------- Bus segment 1 - - - - -
16 | | SCL/SDA | |-------------- | |
17 | |------------| |
19 | Linux | GPIO 1..N | MUX |--------------- Devices
20 | |------------| | | |
22 | | | |---------------| |
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| /linux/include/uapi/linux/ |
| H A D | gpio.h | 1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
3 * <linux/gpio.h> - userspace ABI for the GPIO character devices
21 * Must be a multiple of 8 to ensure 32/64-bit alignment of structs.
26 * struct gpiochip_info - Information about a certain GPIO chip
27 * @name: the Linux kernel name of this GPIO chip
28 * @label: a functional name for this GPIO chip, such as a product
30 * @lines: number of GPIO lines on this chip
41 * Must be no greater than 64, as bitmaps are restricted here to 64-bits
42 * for simplicity, and a multiple of 2 to ensure 32/64-bit alignment of
48 * The maximum number of configuration attributes associated with a line
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| /linux/drivers/pinctrl/qcom/ |
| H A D | pinctrl-qdf2xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * GPIO and pin control functions on this SOC are handled by the "TLMM"
6 * device. The driver which controls this device is pinctrl-msm.c. Each
7 * SOC with a TLMM is expected to create a client driver that registers
8 * with pinctrl-msm.c. This means that all TLMM drivers are pin control
11 * This pin control driver is intended to be used only an ACPI-enabled
14 * a GPIO-only driver. The alternative is to duplicate the GPIO code of
15 * pinctrl-msm.c into another driver.
23 #include "pinctrl-msm.h"
25 /* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */
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| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am65-iot2050-arduino-connector.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2018-2023
13 pinctrl-names =
15 "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown",
16 "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown",
17 "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown",
18 "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown",
19 "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown",
20 "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown",
21 "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown",
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