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/linux/Documentation/devicetree/bindings/soc/xilinx/
H A Dxilinx.yaml49 - xlnx,zynqmp-zc1751
50 - const: xlnx,zynqmp
54 - const: xlnx,zynqmp-zc1232-revA
55 - const: xlnx,zynqmp-zc1232
56 - const: xlnx,zynqmp
60 - const: xlnx,zynqmp-zc1254-revA
61 - const: xlnx,zynqmp-zc1254
62 - const: xlnx,zynqmp
66 - const: xlnx,zynqmp-zcu1275-revA
67 - const: xlnx,zynqmp-zcu1275
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A DMakefile3 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
4 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
5 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
6 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb
7 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb
8 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb
9 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb
10 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
11 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
12 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
[all …]
H A Dzynqmp-smk-k26-revA.dts3 * dts file for Xilinx ZynqMP SMK-K26 rev2/1/B/A
11 #include "zynqmp-sm-k26-revA.dts"
14 model = "ZynqMP SMK-K26 Rev2/1/B/A";
15 compatible = "xlnx,zynqmp-smk-k26-rev2",
16 "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
17 "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
18 "xlnx,zynqmp";
H A Dzynqmp-zcu1275-revA.dts3 * dts file for Xilinx ZynqMP ZCU1275
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
17 model = "ZynqMP ZCU1275 RevA";
18 compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp";
H A Dzynqmp-zc1254-revA.dts3 * dts file for Xilinx ZynqMP ZC1254
13 #include "zynqmp.dtsi"
14 #include "zynqmp-clk-ccf.dtsi"
17 model = "ZynqMP ZC1254 RevA";
18 compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
H A Dzynqmp-zcu102-rev1.1.dts3 * dts file for Xilinx ZynqMP ZCU102 Rev1.1
10 #include "zynqmp-zcu102-rev1.0.dts"
13 model = "ZynqMP ZCU102 Rev1.1";
14 compatible = "xlnx,zynqmp-zcu102-rev1.1", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
H A Dzynqmp-zcu102-rev1.0.dts3 * dts file for Xilinx ZynqMP ZCU102 Rev1.0
10 #include "zynqmp-zcu102-revB.dts"
13 model = "ZynqMP ZCU102 Rev1.0";
14 compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
H A Dzynqmp-zc1232-revA.dts3 * dts file for Xilinx ZynqMP ZC1232
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP ZC1232 RevA";
17 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
H A Dzynqmp-zcu102-revB.dts3 * dts file for Xilinx ZynqMP ZCU102 RevB
11 #include "zynqmp-zcu102-revA.dts"
14 model = "ZynqMP ZCU102 RevB";
15 compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
H A Davnet-ultra96-rev1.dts12 #include "zynqmp-zcu100-revC.dts"
17 "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100",
18 "xlnx,zynqmp";
H A Dzynqmp-zc1751-xm018-dc4.dts3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
12 #include "zynqmp.dtsi"
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
/linux/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
51 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
52 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
[all …]
/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
24 const: xlnx,zynqmp-firmware
60 $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
66 $ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
67 description: The ZynqMP MPSoC provides access to the hardware related data
72 $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml
73 description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
79 $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
[all …]
/linux/Documentation/devicetree/bindings/crypto/
H A Dxlnx,zynqmp-aes.yaml4 $id: http://devicetree.org/schemas/crypto/xlnx,zynqmp-aes.yaml#
7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator
14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
19 const: xlnx,zynqmp-aes
29 zynqmp_firmware: zynqmp-firmware {
30 compatible = "xlnx,zynqmp-firmware";
32 xlnx_aes: zynqmp-aes {
33 compatible = "xlnx,zynqmp-aes";
/linux/Documentation/devicetree/bindings/power/reset/
H A Dxlnx,zynqmp-power.yaml4 $id: http://devicetree.org/schemas/power/reset/xlnx,zynqmp-power.yaml#
13 The zynqmp-power node describes the power management configurations.
18 const: xlnx,zynqmp-power
34 xlnx,zynqmp-ipi-mailbox.txt for typical controller that
59 zynqmp-firmware {
61 compatible = "xlnx,zynqmp-power";
72 zynqmp-firmware {
74 compatible = "xlnx,zynqmp-power";
/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxlnx,zynqmp-dpdma.yaml4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
25 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
29 const: xlnx,zynqmp-dpdma
61 #include <dt-bindings/power/xlnx-zynqmp-power.h>
64 compatible = "xlnx,zynqmp-dpdma";
H A Dxlnx,zynqmp-dma-1.0.yaml4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
29 - xlnx,zynqmp-dma-1.0
78 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
81 compatible = "xlnx,zynqmp-dma-1.0";
/linux/Documentation/devicetree/bindings/phy/
H A Dxlnx,zynqmp-psgtr.yaml4 $id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
7 title: Xilinx ZynqMP Gigabit Transceiver PHY
13 This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
43 - xlnx,zynqmp-psgtr-v1.1
44 - xlnx,zynqmp-psgtr
85 const: xlnx,zynqmp-psgtr-v1.1
96 compatible = "xlnx,zynqmp-psgtr-v1.1";
/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-xilinx.yaml17 - xlnx,zynqmp-dwc3
101 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
102 #include <dt-bindings/power/xlnx-zynqmp-power.h>
103 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
104 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
105 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
114 compatible = "xlnx,zynqmp-dwc3";
/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,zynqmp-pcap-fpga.yaml4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
14 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
20 const: xlnx,zynqmp-pcap-fpga
30 zynqmp_firmware: zynqmp-firmware {
32 compatible = "xlnx,zynqmp-pcap-fpga";
/linux/Documentation/devicetree/bindings/gpio/
H A Dxlnx,zynqmp-gpio-modepin.yaml4 $id: http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
7 title: ZynqMP Mode Pin GPIO controller
20 const: xlnx,zynqmp-gpio-modepin
38 zynqmp-firmware {
40 compatible = "xlnx,zynqmp-gpio-modepin";
/linux/Documentation/devicetree/bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.yaml4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
15 | Xilinx ZynqMP IPI Controller |
41 - xlnx,zynqmp-ipi-mailbox
88 - xlnx,zynqmp-ipi-dest-mailbox
115 - xlnx,zynqmp-ipi-dest-mailbox
161 - xlnx,zynqmp-ipi-mailbox
192 zynqmp-mailbox {
193 compatible = "xlnx,zynqmp-ipi-mailbox";
201 compatible = "xlnx,zynqmp-ipi-dest-mailbox";
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
22 - xlnx,zynqmp-r5fss
80 - xlnx,zynqmp-r5f
193 - xlnx,zynqmp-r5fss
274 #include <dt-bindings/power/xlnx-zynqmp-power.h>
282 compatible = "xlnx,zynqmp-r5fss";
294 compatible = "xlnx,zynqmp-r5f";
307 compatible = "xlnx,zynqmp-r5f";
328 compatible = "xlnx,zynqmp-r5fss";
340 compatible = "xlnx,zynqmp-r5f";
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
103 Recommended with ZynqMP, specify reset control for this
104 controller instance with zynqmp-reset driver.
200 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
201 #include <dt-bindings/power/xlnx-zynqmp-power.h>
202 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
209 compatible = "xlnx,zynqmp-gem", "cdns,gem";
/linux/Documentation/devicetree/bindings/nvmem/
H A Dxlnx,zynqmp-nvmem.yaml4 $id: http://devicetree.org/schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
10 The ZynqMP MPSoC provides access to the hardware related data
22 const: xlnx,zynqmp-nvmem-fw
32 compatible = "xlnx,zynqmp-nvmem-fw";

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