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/linux/arch/arm/boot/dts/xilinx/
H A DMakefile3 zynq-cc108.dtb \
4 zynq-ebaz4205.dtb \
5 zynq-microzed.dtb \
6 zynq-parallella.dtb \
7 zynq-zc702.dtb \
8 zynq-zc706.dtb \
9 zynq-zc770-xm010.dtb \
10 zynq-zc770-xm011.dtb \
11 zynq-zc770-xm012.dtb \
12 zynq-zc770-xm013.dtb \
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H A Dzynq-7000.dtsi9 compatible = "xlnx,zynq-7000";
111 compatible = "xlnx,zynq-xadc-1.00.a";
119 compatible = "xlnx,zynq-can-1.0";
131 compatible = "xlnx,zynq-can-1.0";
143 compatible = "xlnx,zynq-gpio-1.0";
197 compatible = "xlnx,zynq-ddrc-a05";
231 compatible = "xlnx,zynq-spi-r1p6";
243 compatible = "xlnx,zynq-spi-r1p6";
255 compatible = "xlnx,zynq-qspi-1.0";
267 compatible = "xlnx,zynq-gem", "cdns,gem";
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H A Dzynq-zturn.dts4 /include/ "zynq-zturn-common.dtsi"
7 model = "Zynq Z-Turn MYIR Board";
8 compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
H A Dzynq-zturn-v5.dts4 /include/ "zynq-zturn-common.dtsi"
7 model = "Zynq Z-Turn MYIR Board V5";
8 compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000";
H A Dzynq-zybo-z7.dts3 #include "zynq-7000.dtsi"
8 compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
31 label = "zynq-zybo-z7:green:ld4";
H A Dzynq-microzed.dts7 /include/ "zynq-7000.dtsi"
11 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
H A Dzynq-zed.dts7 #include "zynq-7000.dtsi"
11 compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000";
H A Dzynq-zybo.dts7 #include "zynq-7000.dtsi"
11 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
H A Dzynq-parallella.dts5 * Derived from zynq-zed.dts:
12 /include/ "zynq-7000.dtsi"
16 compatible = "adapteva,parallella", "xlnx,zynq-7000";
H A Dzynq-zc770-xm011.dts8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
11 This should be a phandle to the Zynq's SLCR registers.
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
H A Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
13 The Zynq UltraScale+ MPSoC and Versal has several different resets.
24 For list of all valid reset indices for Zynq UltraScale+ MPSoC
/linux/drivers/net/can/ctucanfd/
H A DKconfig7 The core integration to Xilinx Zynq system as platform driver
8 is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top).
30 modified to be CAN FD frames tolerant on MicroZed Zynq based
32 company. FPGA design https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top.
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dxlnx,zynq-ddrc-a05.yaml4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
7 title: Zynq A05 DDR Memory Controller
14 The Zynq DDR ECC controller has an optional ECC support in half-bus width
20 const: xlnx,zynq-ddrc-a05
34 compatible = "xlnx,zynq-ddrc-a05";
/linux/Documentation/devicetree/bindings/spi/
H A Dxlnx,zynq-qspi.yaml4 $id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
7 title: Xilinx Zynq QSPI controller
10 The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
22 const: xlnx,zynq-qspi-1.0
52 compatible = "xlnx,zynq-qspi-1.0";
/linux/Documentation/devicetree/bindings/clock/
H A Dzynq-7000.txt1 Device Tree Clock bindings for the Zynq 7000 EPP
3 The Zynq EPP has several different clk providers, each with there own bindings.
7 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
19 (usually 33 MHz oscillators are used for Zynq platforms)
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-zynq.yaml4 $id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml#
7 title: Xilinx Zynq GPIO controller
15 - xlnx,zynq-gpio-1.0
63 - xlnx,zynq-gpio-1.0
108 compatible = "xlnx,zynq-gpio-1.0";
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dxilinx-xadc.txt8 frontends for the DRP interface exist. One that is only available on the ZYNQ
9 family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
32 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
88 compatible = "xlnx,zynq-xadc-1.00.a";
/linux/arch/arm/mach-zynq/
H A Dcommon.c15 #include <linux/clk/zynq.h>
59 .name = "cpuidle-zynq",
63 * zynq_get_revision - Get Zynq silicon revision
73 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0"); in zynq_get_revision()
117 soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq"); in zynq_init_machine()
184 "xlnx,zynq-7000",
188 DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
/linux/Documentation/devicetree/bindings/fpga/
H A Dxilinx-zynq-fpga-mgr.yaml4 $id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
7 title: Xilinx Zynq FPGA Manager
14 const: xlnx,zynq-devcfg-1.0
46 compatible = "xlnx,zynq-devcfg-1.0";
/linux/Documentation/devicetree/bindings/net/can/
H A Dctu,ctucanfd.yaml16 Integration in Xilinx Zynq SoC based system together with
18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
48 for FPGA implementation on Zynq-7000 system).
H A Dxilinx,can.yaml16 - xlnx,zynq-can-1.0
39 description: CAN Tx fifo depth (Zynq, Axi CAN).
43 description: CAN Rx fifo depth (Zynq, Axi CAN, CAN FD in sequential Rx mode)
72 - xlnx,zynq-can-1.0
124 compatible = "xlnx,zynq-can-1.0";
/linux/drivers/firmware/xilinx/
H A DKconfig4 menu "Zynq MPSoC Firmware Drivers"
8 bool "Enable Xilinx Zynq MPSoC firmware interface"
20 bool "Enable Xilinx Zynq MPSoC firmware debug APIs"
/linux/drivers/cpuidle/
H A Dcpuidle-zynq.c5 * CPU idle support for Xilinx Zynq
54 pr_info("Xilinx Zynq CpuIdle Driver started\n"); in zynq_cpuidle_probe()
61 .name = "cpuidle-zynq",
/linux/drivers/gpio/
H A Dgpio-zynq.c3 * Xilinx Zynq GPIO device driver
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
99 /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
137 * struct zynq_platform_data - zynq gpio platform data structure
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