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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dxilinx.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Platforms
10 - Michal Simek <michal.simek@amd.com>
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
20 - items:
21 - enum:
22 - adapteva,parallella
23 - digilent,zynq-zybo
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/xilinx/
H A Dxilinx.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Platforms
10 - Michal Simek <michal.simek@amd.com>
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
20 - items:
21 - enum:
22 - adapteva,parallella
23 - digilent,zynq-zybo
[all …]
/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-zed.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000";
26 stdout-path = "serial0:115200n8";
30 compatible = "usb-nop-xceiv";
31 #phy-cells = <0>;
36 ps-clk-frequency = <33333333>;
41 phy-mode = "rgmii-id";
[all …]
H A Dzynq-zybo-z7.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "zynq-7000.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
8 compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
22 stdout-path = "serial0:115200n8";
25 gpio-leds {
26 compatible = "gpio-leds";
28 led-ld4 {
29 label = "zynq-zybo-z7:green:ld4";
[all …]
H A Dzynq-microzed.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 /include/ "zynq-7000.dtsi"
11 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
25 stdout-path = "serial0:115200n8";
29 compatible = "usb-nop-xceiv";
30 #phy-cells = <0>;
35 ps-clk-frequency = <33333333>;
40 phy-mode = "rgmii-id";
[all …]
H A Dzynq-zybo.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
26 stdout-path = "serial0:115200n8";
30 #phy-cells = <0>;
31 compatible = "usb-nop-xceiv";
32 reset-gpios = <&gpio0 46 1>;
37 ps-clk-frequency = <50000000>;
[all …]
H A Dzynq-zc770-xm011.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013-2018 Xilinx, Inc.
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
22 stdout-path = "serial0:115200n8";
31 compatible = "usb-nop-xceiv";
32 #phy-cells = <0>;
42 clock-frequency = <400000>;
52 num-cs = <4>;
[all …]
H A Dzynq-zc770-xm012.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013-2018 Xilinx, Inc.
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
38 clock-frequency = <400000>;
48 clock-frequency = <400000>;
58 num-cs = <4>;
59 is-decoded-cs = <0>;
H A Dzynq-cc108.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2018 Xilinx, Inc.
6 * (C) Copyright 2007-2013 Michal Simek
7 * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
11 /dts-v1/;
12 /include/ "zynq-7000.dtsi"
16 compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000";
25 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
[all …]
H A Dzynq-zc770-xm013.dts1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
38 phy-mode = "rgmii-id";
39 phy-handle = <&ethernet_phy>;
41 ethernet_phy: ethernet-phy@7 {
43 device_type = "ethernet-phy";
49 clock-frequency = <400000>;
[all …]
H A Dzynq-parallella.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Derived from zynq-zed.dts:
11 /dts-v1/;
12 /include/ "zynq-7000.dtsi"
16 compatible = "adapteva,parallella", "xlnx,zynq-7000";
30 stdout-path = "serial0:115200n8";
35 fclk-enable = <0xf>;
36 ps-clk-frequency = <33333333>;
41 phy-mode = "rgmii-id";
42 phy-handle = <&ethernet_phy>;
[all …]
H A Dzynq-zc770-xm010.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2013-2018 Xilinx, Inc.
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
23 stdout-path = "serial0:115200n8";
32 compatible = "usb-nop-xceiv";
33 #phy-cells = <0>;
43 phy-mode = "rgmii-id";
44 phy-handle = <&ethernet_phy>;
[all …]
H A Dzynq-zturn-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * Based on zynq-zed.dts which is:
7 * Copyright (C) 2011 - 2014 Xilinx
12 /dts-v1/;
13 /include/ "zynq-7000.dtsi"
16 compatible = "xlnx,zynq-7000";
31 stdout-path = "serial0:115200n8";
34 gpio-leds {
35 compatible = "gpio-leds";
36 usr-led1 {
[all …]
H A Dzynq-zturn-v5.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
4 /include/ "zynq-zturn-common.dtsi"
7 model = "Zynq Z-Turn MYIR Board V5";
8 compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000";
12 ethernet_phy: ethernet-phy@0 {
H A Dzynq-zturn.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
4 /include/ "zynq-zturn-common.dtsi"
7 model = "Zynq Z-Turn MYIR Board";
8 compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
12 ethernet_phy: ethernet-phy@0 {
/freebsd/share/man/man4/
H A Dcgem.435 .Bd -ragged -offset indent
45 the Xilinx Zynq-7000, the Xilinx Zynq UltraScale+, and the SiFive
51 .Bl -tag -width ".Cm 10baseT/UTP"
65 .Cm full-duplex
67 .Cm half-duplex
75 .Cm full-duplex
77 .Cm half-duplex
82 .Cm full-duplex
89 .Bl -tag -width ".Cm full-duplex"
90 .It Cm full-duplex
[all …]
/freebsd/sys/arm/xilinx/
H A Dzy7_gpio.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * A GPIO driver for Xilinx Zynq-7000.
32 * The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os.
34 * Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are
35 * available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of
36 * Zynq as EMIO signals.
41 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
71 /* Zynq 7000 */
103 #define ZYNQ_BANK_NPIN(type, bank) (ZYNQ##type##_BANK##bank##_NPIN)
[all …]
H A Dzy7_machdep.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Machine dependent code for Xilinx Zynq-7000 Soc.
32 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
60 * Set up static device mappings. Not strictly necessary -- simplebus will
61 * dynamically establish mappings as needed -- but doing it this way gets us
99 FDT_PLATFORM_DEF(zynq7, "zynq7", 0, "xlnx,zynq-7000", 200);
H A Dzy7_reg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2012-2013 Thomas Skibo
30 * Address regions of Zynq-7000.
31 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
H A Dzy7_slcr.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
66 #define ZSLCR_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
67 #define ZSLCR_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
69 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
71 #define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
73 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
74 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
[all …]
/freebsd/sys/dts/arm/
H A Dzynq-7000.dtsi1 /*-
29 compatible = "xlnx,zynq-7000";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 interrupt-parent = <&GIC>;
38 // Zynq PS System registers.
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
48 slcr: slcr@7000 {
[all …]
H A Dzedboard.dts1 /*-
27 /dts-v1/;
28 /include/ "zynq-7000.dtsi"
32 compatible = "digilent,zedboard", "xlnx,zynq-7000";
47 clock-frequency = <33333333>; // 33Mhz PS_CLK
51 clock-frequency = <333333333>; // 333Mhz
67 spi-chipselect = <0>;
H A Dzybo.dts1 /*-
27 /dts-v1/;
28 /include/ "zynq-7000.dtsi"
32 compatible = "digilent,zybo", "xlnx,zynq-7000";
47 clock-frequency = <50000000>; // 50Mhz PS_CLK
51 clock-frequency = <325000000>; // 325Mhz
67 spi-chipselect = <0>;
/freebsd/share/man/man4/man4.arm/
H A Ddevcfg.430 .Nd Zynq PL device config interface
36 can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.
41 asserts the top-level PL reset signals, disables the PS-PL level shifters,
45 shifters and release the top-level PL reset signals.
49 .Bd -literal -offset indent
59 .Bd -literal -offset indent
60 promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin
68 .Bl -tag -width 4n
75 This variable controls if the PS-PL level shifters are enabled after the
84 .Bl -tag -width 12n
[all …]
/freebsd/sys/arm/conf/
H A DZEDBOARD2 # ZEDBOARD -- Custom configuration for the Xilinx Zynq-7000 based
3 # ZedBoard (www.zedboard.org) and similar Zynq boards.
8 # https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config
26 makeoptions MODULES_EXTRA="dtb/zynq"
70 device zy7_qspi # Xilinx Zynq QSPI controller
71 device zy7_spi # Xilinx Zynq SPI controller
85 device axe # USB-Ethernet

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