Searched full:zve32x (Results 1 – 8 of 8) sorted by relevance
/freebsd/sys/contrib/device-tree/Bindings/riscv/ |
H A D | extensions.yaml | 446 - const: zve32x 448 The standard Zve32x extension for embedded processors, as ratified
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/freebsd/contrib/llvm-project/clang/lib/Sema/ |
H A D | SemaRISCV.cpp | 1400 // if we don't have at least zve32x supported, then we need to emit error. in checkRVVTypeSupport() 1401 else if (!FeatureMap.lookup("zve32x")) in checkRVVTypeSupport() 1402 Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32x"; in checkRVVTypeSupport()
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H A D | SemaType.cpp | 8303 if (!S.Context.getTargetInfo().hasFeature("zve32x")) { in HandleRISCVRVVVectorBitsTypeAttr() 8305 << Attr << "'zve32x'"; in HandleRISCVRVVVectorBitsTypeAttr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVFeatures.td | 661 : RISCVExtension<"zve32x", 1, 0, 662 "'Zve32x' (Vector Extensions for Embedded Processors " 855 "'V' (Vector Extension for Application Processors), 'Zve32x' "
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H A D | RISCVISelLowering.cpp | 4961 // We might have a RotateVT that isn't legal, e.g. v4i64 on zve32x. in isLegalBitRotate()
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/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/ |
H A D | RISCV.cpp | 203 if (ISAInfo->hasExtension("zve32x")) { in getTargetDefines()
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/freebsd/contrib/llvm-project/clang/utils/TableGen/ |
H A D | RISCVVEmitter.cpp | 425 "ATTRS, \"zve32x\")\n"; in createBuiltins()
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/ |
H A D | RISCVISAInfo.cpp | 731 bool HasVector = Exts.count("zve32x") != 0; in checkDependency()
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