| /freebsd/sys/contrib/device-tree/src/riscv/sophgo/ |
| H A D | sg2044-cpus.dtsi | 32 "zawrs", "zba", "zbb", "zbc", 68 "zawrs", "zba", "zbb", "zbc", 104 "zawrs", "zba", "zbb", "zbc", 140 "zawrs", "zba", "zbb", "zbc", 176 "zawrs", "zba", "zbb", "zbc", 212 "zawrs", "zba", "zbb", "zbc", 248 "zawrs", "zba", "zbb", "zbc", 284 "zawrs", "zba", "zbb", "zbc", 320 "zawrs", "zba", "zbb", "zbc", 356 "zawrs", "zba", "zbb", "zbc", [all …]
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| /freebsd/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/funcs/ |
| H A D | tst.strstr.d | 52 strstr(str, "baz"), strstr(str, "zba"), 53 strstr(strstr(str, "baz"), strstr(str, "zba")));
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| /freebsd/sys/net/ |
| H A D | bpf_zerocopy.c | 528 struct zbuf *zba, *zbb; in bpf_zerocopy_ioctl_setzbuf() local 551 &zba); in bpf_zerocopy_ioctl_setzbuf() 557 zbuf_free(zba); in bpf_zerocopy_ioctl_setzbuf() 569 zbuf_free(zba); in bpf_zerocopy_ioctl_setzbuf() 575 * Point BPF descriptor at buffers; initialize sbuf as zba so that in bpf_zerocopy_ioctl_setzbuf() 579 d->bd_sbuf = (caddr_t)zba; in bpf_zerocopy_ioctl_setzbuf()
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| /freebsd/sys/contrib/device-tree/src/riscv/spacemit/ |
| H A D | k1.dtsi | 60 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 90 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 120 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 150 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 180 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 210 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 240 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 270 "zifencei", "zihintpause", "zihpm", "zfh", "zba",
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| /freebsd/crypto/openssl/doc/man3/ |
| H A D | OPENSSL_riscvcap.pod | 33 zba/zbb/zbs would not be implied in the capability vector. 39 =item ZBA
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVScheduleZb.td | 11 // Zba extension 50 // Zba extension
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| H A D | RISCVSchedXiangShanNanHu.td | 78 // Zba 277 // Zba
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| H A D | RISCVSchedMIPSP8700.td | 51 // Handle zba.
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| H A D | RISCVSchedGenericOOO.td | 231 // Zba extension 429 // Zba extension
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| H A D | RISCVSchedSyntacoreSCR7.td | 85 // Zba
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| H A D | RISCVSchedAndes45.td | 195 // Zba extension
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| H A D | RISCVFeatures.td | 475 "'Zba' (Address Generation Instructions)">; 504 : RISCVExtension<1, 0, "the collection of the Zba, Zbb, Zbs extensions", 1081 "'Zba' (Address Generation Instructions) or "
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| H A D | RISCVInstrInfoZb.td | 11 // Zba - 1.0
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| H A D | RISCVISelDAGToDAG.cpp | 221 // If we have Zba we can use (ADD_UW X, (SLLI X, 32)) to handle cases where in selectImm() 1209 // - with Zba it's just (slli.uw X, C) in Select() 1210 // - without Zba a tablegen pattern applies the very same in Select()
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| H A D | RISCVInstrInfo.cpp | 4505 // We can use Zba SHXADD+SLLI instructions for multiply in some cases. in mulImm()
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| /freebsd/secure/lib/libcrypto/man/man3/ |
| H A D | OPENSSL_riscvcap.3 | 100 .IP ZBA 4 101 .IX Item "ZBA"
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| /freebsd/crypto/openssl/include/crypto/ |
| H A D | riscv_arch.def | 29 RISCV_DEFINE_CAP(ZBA, 0, 0, 4, (1 << 3))
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| /freebsd/usr.sbin/bsdinstall/partedit/ |
| H A D | diskmenu.c | 70 "[\\Z1\\ZbA\\Znuto]: guided partitioning tool.\n" in diskmenu_show()
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| /freebsd/sys/contrib/device-tree/src/riscv/starfive/ |
| H A D | jh7110.dtsi | 32 riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr", 61 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", 94 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", 127 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", 160 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 239 // If we have exactly 32 leading zeros and Zba, we can try using zext.w at in generateInstSeqLeadingZeros() 394 // Perform optimization with SH*ADD in the Zba extension. in generateInstSeq() 528 // If we have Zba, we can use (ADD_UW X, (SLLI X, 32)). in generateTwoRegInstSeq()
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| /freebsd/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | extensions.yaml | 258 - const: zba 260 The standard Zba bit-manipulation extension for address generation
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| /freebsd/contrib/llvm-project/compiler-rt/lib/builtins/cpu_model/ |
| H A D | riscv.c | 291 SET_RISCV_HWPROBE_EXT_SINGLE_RISCV_FEATURE(ZBA); in initRISCVFeature()
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| /freebsd/contrib/llvm-project/llvm/lib/TargetParser/ |
| H A D | RISCVISAInfo.cpp | 161 // (e.g. zba1p0 is extension 'zba' of version '1p0'). So the function will
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| H A D | Host.cpp | 2223 Features["zba"] = ExtMask & (1 << 3); // RISCV_HWPROBE_EXT_ZBA in getHostCPUFeatures()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVLegalizerInfo.cpp | 833 // If we have Zba we can use (ADD_UW X, (SLLI X, 32)) to handle cases where in shouldBeInConstantPool()
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