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/linux/drivers/net/ethernet/xilinx/
H A DKconfig3 # Xilinx device configuration
7 bool "Xilinx devices"
14 the questions about Xilinx devices. If you say Y, you will be asked
20 tristate "Xilinx 10/100 Ethernet Lite support"
24 This driver supports the 10/100 Ethernet Lite from Xilinx.
27 tristate "Xilinx 10/100/1000 AXI Ethernet support"
32 This driver supports the 10/100/1000 Ethernet from Xilinx for the
33 AXI bus interface used in Xilinx Virtex FPGAs and Soc's.
36 tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver"
40 This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
[all …]
/linux/Documentation/devicetree/bindings/
H A Dxilinx.txt1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
4 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
89 That covers the general approach to binding xilinx IP cores into the
92 i) Xilinx ML300 Framebuffer
105 ii) Xilinx SystemACE
107 The Xilinx SystemACE device is used to program FPGAs from an FPGA
114 iii) Xilinx EMAC and Xilinx TEMAC
116 Xilinx Ethernet devices. In addition to general xilinx properties
121 iv) Xilinx Uartlite
[all …]
/linux/Documentation/devicetree/bindings/soc/xilinx/
H A Dxilinx.yaml4 $id: http://devicetree.org/schemas/soc/xilinx/xilinx.yaml#
7 title: Xilinx Zynq Platforms
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
52 - description: Xilinx internal board zc1232
58 - description: Xilinx internal board zc1254
64 - description: Xilinx evaluation board zcu1275
70 - description: Xilinx 96boards compatible board zcu100
76 - description: Xilinx 96boards compatible board Ultra96
84 - description: Xilinx evaluation board zcu102
94 - description: Xilinx evaluation board zcu104
[all …]
/linux/drivers/media/platform/xilinx/
H A DKconfig3 comment "Xilinx media platform drivers"
6 tristate "Xilinx Video IP (EXPERIMENTAL)"
14 Driver for Xilinx Video IP Pipelines
18 tristate "Xilinx CSI-2 Rx Subsystem"
20 Driver for Xilinx MIPI CSI-2 Rx Subsystem. This is a V4L sub-device
25 tristate "Xilinx Video Test Pattern Generator"
29 Driver for the Xilinx Video Test Pattern Generator
32 tristate "Xilinx Video Timing Controller"
35 Driver for the Xilinx Video Timing Controller
H A DMakefile3 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
5 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
6 obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
7 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
8 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
H A Dxilinx-vipp.h3 * Xilinx Video IP Composite Device
6 * Copyright (C) 2013-2015 Xilinx, Inc.
8 * Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
23 * struct xvip_composite_device - Xilinx Video IP device structure
/linux/sound/soc/xilinx/
H A DKconfig3 tristate "Audio support for the Xilinx I2S"
5 Select this option to enable Xilinx I2S Audio. This enables
6 I2S playback and capture using xilinx soft IP. In transmitter
12 tristate "Audio support for the Xilinx audio formatter"
14 Select this option to enable Xilinx audio formatter
19 tristate "Audio support for the Xilinx SPDIF"
21 Select this option to enable Xilinx SPDIF Audio.
/linux/Documentation/ABI/stable/
H A Dsysfs-driver-firmware-zynqmp4 Contact: "Jolly Shah" <jollys@xilinx.com>
13 other Xilinx software products: GLOBAL_GEN_STORAGE{4:6}.
25 Users: Xilinx
30 Contact: "Jolly Shah" <jollys@xilinx.com>
40 Four registers are used by the FSBL and other Xilinx
54 Users: Xilinx
59 Contact: "Jolly Shah" <jollys@xilinx.com>
91 Users: Xilinx
96 Contact: "Jolly Shah" <jollys@xilinx.com>
115 Users: Xilinx
[all …]
/linux/drivers/irqchip/
H A Dirq-xilinx-intc.c3 * Copyright (C) 2012-2013 Xilinx, Inc.
69 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); in intc_enable_or_unmask()
85 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); in intc_disable_or_mask()
93 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); in intc_ack()
102 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); in intc_mask_ack()
108 .name = "Xilinx INTC",
182 pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n"); in xilinx_intc_of_init()
188 pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n"); in xilinx_intc_of_init()
193 pr_warn("irq-xilinx: mismatch in kind-of-intr param\n"); in xilinx_intc_of_init()
195 pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n", in xilinx_intc_of_init()
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dxilinx-xadc.txt1 Xilinx XADC device driver
3 This binding document describes the bindings for the Xilinx 7 Series XADC as well
6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
14 The Xilinx System Monitor is an ADC that is found in the UltraScale and
15 UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
16 communication. Xilinx provides a standard IP core that can be used to access the
18 called the Xilinx System Management Wizard. This document describes the bindings
28 Xilinx System Management Wizard fabric IP core to access the
/linux/drivers/net/ethernet/sfc/
H A Def100.c5 * Copyright 2019-2022 Xilinx Inc.
32 /* Expected size of a Xilinx continuation address table entry. */
86 "Bad BAR value of %d in Xilinx capabilities EF100 entry.\n", in ef100_pci_parse_ef100_entry()
104 /* Parse a Xilinx capabilities table entry describing a continuation to a new
128 "Bad BAR value of %d in Xilinx capabilities sub-table.\n", in ef100_pci_parse_continue_entry()
138 "Xilinx table will overrun BAR[%d] offset=0x%llx\n", in ef100_pci_parse_continue_entry()
149 "Mapping new BAR for Xilinx table failed, rc=%d\n", rc); in ef100_pci_parse_continue_entry()
175 /* Iterate over the Xilinx capabilities table in the currently mapped BAR and
197 "Seen Xilinx table entry 0x%x size 0x%x at 0x%llx in BAR[%d]\n", in ef100_pci_walk_xilinx_table()
202 "Xilinx table entry too short len=0x%x\n", entry_size); in ef100_pci_walk_xilinx_table()
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/linux/drivers/char/xilinx_hwicap/
H A Dfifo_icap.h3 * Author: Xilinx, Inc.
10 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
12 * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
14 * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
17 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
24 * (c) Copyright 2007-2008 Xilinx Inc.
H A Dbuffer_icap.h3 * Author: Xilinx, Inc.
10 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
12 * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
14 * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
17 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
24 * (c) Copyright 2003-2008 Xilinx Inc.
/linux/sound/pci/mixart/
H A Dmixart_hwdep.c343 /* read motherboard xilinx status */ in mixart_dsp_load()
347 /* read daughterboard xilinx status */ in mixart_dsp_load()
350 /* motherboard xilinx status 5 will say that the board is performing a reset */ in mixart_dsp_load()
359 /* xilinx already loaded ? */ in mixart_dsp_load()
361 dev_dbg(&mgr->pci->dev, "xilinx is already loaded !\n"); in mixart_dsp_load()
367 "xilinx load error ! status = %d\n", in mixart_dsp_load()
372 /* check xilinx validity */ in mixart_dsp_load()
378 /* set xilinx status to copying */ in mixart_dsp_load()
381 /* setup xilinx base address */ in mixart_dsp_load()
383 /* setup code size for xilinx file */ in mixart_dsp_load()
[all …]
/linux/drivers/staging/axis-fifo/
H A DKconfig3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
/linux/drivers/firmware/xilinx/
H A Dzynqmp-debug.h3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2018 Xilinx
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
/linux/drivers/soc/xilinx/
H A DKconfig2 menu "Xilinx SoC drivers"
5 bool "Enable Xilinx Zynq MPSoC Power Management driver"
20 bool "Enable Xilinx Event Management Driver"
24 Say yes to enable event management support for Xilinx.
/linux/drivers/clk/xilinx/
H A DKconfig4 tristate "Xilinx VCU logicoreIP Init"
21 tristate "Xilinx Clocking Wizard"
25 Support for the Xilinx Clocking Wizard IP core clock generator.
27 This driver supports the Xilinx clocking wizard programmable clock
/linux/drivers/fpga/
H A Dversal-fpga.c3 * Copyright (C) 2019-2021 Xilinx, Inc.
57 mgr = devm_fpga_mgr_register(dev, "Xilinx Versal FPGA Manager", in versal_fpga_probe()
77 MODULE_AUTHOR("Nava kishore Manne <nava.manne@xilinx.com>");
78 MODULE_AUTHOR("Appana Durga Kedareswara rao <appanad.durga.rao@xilinx.com>");
79 MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
H A Dxilinx-pr-decoupler.c4 * Copyright (c) 2017, Xilinx Inc
6 * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
87 .name = "Xilinx PR Decoupler",
91 .name = "Xilinx DFX AXI Shutdown Manager",
174 MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
176 MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
/linux/drivers/usb/host/
H A Dehci-xilinx-of.c5 * Bus Glue for Xilinx EHCI core on the of_platform bus
7 * Copyright (c) 2009 Xilinx, Inc.
27 * This function is used as a place to tell the user that the Xilinx USB host
112 * host controller. Because the Xilinx USB host controller can be configured
131 dev_dbg(&op->dev, "initializing XILINX-OF USB Controller\n"); in ehci_hcd_xilinx_of_probe()
138 "XILINX-OF USB"); in ehci_hcd_xilinx_of_probe()
208 dev_dbg(&op->dev, "stopping XILINX-OF USB Controller\n"); in ehci_hcd_xilinx_of_remove()
226 .name = "xilinx-of-ehci",
/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,fpga-slave-serial.yaml7 title: Xilinx Slave Serial SPI FPGA
13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
19 https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
20 https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
21 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
/linux/include/uapi/linux/
H A Dxilinx-v4l2-controls.h3 * Xilinx Controls Header
6 * Copyright (C) 2013-2015 Xilinx, Inc.
8 * Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
30 * Private Controls for Xilinx Video IPs
34 * Xilinx TPG Video IP
/linux/drivers/pci/controller/
H A DKconfig312 bool "Xilinx AXI PCIe controller"
316 Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
320 bool "Xilinx DMA PL PCIe host bridge support"
325 Say 'Y' here if you want kernel support for the Xilinx PL DMA
327 Root Port. If your system provides Xilinx PCIe host controller
331 bool "Xilinx NWL PCIe controller"
335 Say 'Y' here if you want kernel support for Xilinx
341 bool "Xilinx Versal CPM PCI controller"
346 Xilinx Versal CPM host bridge.
/linux/drivers/cpuidle/
H A Dcpuidle-zynq.c3 * Copyright (C) 2012-2013 Xilinx
5 * CPU idle support for Xilinx Zynq
14 * Maintainer: Michal Simek <michal.simek@xilinx.com>
54 pr_info("Xilinx Zynq CpuIdle Driver started\n"); in zynq_cpuidle_probe()

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