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/linux/sound/soc/codecs/
H A Dmt6351.h12 #define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000)
13 #define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002)
14 #define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004)
15 #define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006)
16 #define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008)
17 #define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a)
18 #define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c)
19 #define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e)
20 #define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010)
21 #define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012)
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23.dtsi59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
73 reg = <0x80008000 0x2000>;
81 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
93 reg = <0x80010000 0x2000>;
102 reg = <0x80014000 0x2000>;
110 reg = <0x80018000 0x2000>;
411 reg = <0x80020000 0x2000>;
417 reg = <0x80024000 0x2000>;
433 reg = <0x80028000 0x2000>;
[all …]
H A Dimx28.dtsi70 reg = <0x80000000 0x2000>;
74 reg = <0x80002000 0x2000>;
83 reg = <0x80004000 0x2000>;
103 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
119 reg = <0x80010000 0x2000>;
130 reg = <0x80012000 0x2000>;
141 reg = <0x80014000 0x2000>;
152 reg = <0x80016000 0x2000>;
164 reg = <0x80018000 0x2000>;
993 reg = <0x8001c000 0x2000>;
[all …]
/linux/drivers/clk/axs10x/
H A Di2s_pll_clock.c34 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
35 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
36 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
37 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
38 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
39 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
40 { 2116800, 0x82, 0x3CF, 0x10C30, 0x2000 },
41 { 2304000, 0x104, 0x79E, 0x10B2C, 0x2000 },
47 { 1024000, 0x82, 0x105, 0x107DF, 0x2000 },
48 { 1411200, 0x28A, 0x1, 0x10001, 0x2000 },
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam57-pruss.dtsi37 reg = <0x0 0x2000>,
38 <0x2000 0x2000>,
46 reg = <0x26000 0x2000>;
49 ranges = <0x0 0x26000 0x2000>;
71 reg = <0x20000 0x2000>;
146 reg = <0x0 0x2000>,
147 <0x2000 0x2000>,
155 reg = <0x26000 0x2000>;
158 ranges = <0x0 0x26000 0x2000>;
180 reg = <0x20000 0x2000>;
/linux/Documentation/devicetree/bindings/devfreq/event/
H A Dsamsung,exynos-ppmu.yaml80 reg = <0x106a0000 0x2000>;
103 reg = <0x112a0000 0x2000>;
118 reg = <0x10480000 0x2000>;
123 reg = <0x10490000 0x2000>;
134 reg = <0x104a0000 0x2000>;
139 reg = <0x104b0000 0x2000>;
144 reg = <0x104c0000 0x2000>;
149 reg = <0x104d0000 0x2000>;
158 reg = <0x106a0000 0x2000>;
/linux/drivers/reset/
H A Dreset-uniphier.c44 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
45 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
50 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
51 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
52 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
53 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
54 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
56 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
58 UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */
59 UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
[all …]
/linux/arch/mips/include/asm/mach-db1x00/
H A Dbcsr.h128 #define BCSR_STATUS_DB1000_SWAPBOOT 0x2000
132 #define BCSR_STATUS_DB1200_U1RXD 0x2000 /* DB1200 */
135 #define BCSR_STATUS_DB1550_U3RXD 0x2000 /* DB1550 */
137 #define BCSR_STATUS_PB1550_U1RXD 0x2000 /* PB1550 */
141 #define BCSR_STATUS_USBOCn 0x2000 /* DB1300 */
150 #define BCSR_RESETS_FIR_SEL 0x2000
153 #define BCSR_RESETS_PB1550_WSCFSM 0x2000
169 #define BCSR_BOARD_SPISEL 0x2000 /* PB/DB1550 */
184 #define BCSR_RESETS_PSC1MUX 0x2000
192 #define BCSR_RESETS_OTPCSB 0x2000 /* DB1300 */
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv40.c80 u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000)); in nv40_ram_prog()
83 if (vbl != nvkm_rd32(device, 0x600808 + (i * 0x2000))) { in nv40_ram_prog()
84 nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01); in nv40_ram_prog()
85 sr1[i] = nvkm_rd08(device, 0x0c03c5 + (i * 0x2000)); in nv40_ram_prog()
100 u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000)); in nv40_ram_prog()
106 u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000)); in nv40_ram_prog()
111 nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01); in nv40_ram_prog()
112 nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20); in nv40_ram_prog()
166 u32 tmp = nvkm_rd32(device, 0x600808 + (i * 0x2000)); in nv40_ram_prog()
171 nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01); in nv40_ram_prog()
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dgaudi2_blocks_linux_driver.h27 #define DCORE0_TPC0_EML_STM_SECTION 0x2000
264 #define DCORE0_TPC1_EML_STM_SECTION 0x2000
501 #define DCORE0_TPC2_EML_STM_SECTION 0x2000
738 #define DCORE0_TPC3_EML_STM_SECTION 0x2000
975 #define DCORE0_TPC4_EML_STM_SECTION 0x2000
1212 #define DCORE0_TPC5_EML_STM_SECTION 0x2000
1449 #define DCORE0_TPC6_EML_STM_SECTION 0x2000
1686 #define DCORE1_TPC0_EML_STM_SECTION 0x2000
1923 #define DCORE1_TPC1_EML_STM_SECTION 0x2000
2160 #define DCORE1_TPC2_EML_STM_SECTION 0x2000
[all …]
/linux/arch/arm64/boot/dts/actions/
H A Ds700.dtsi108 <0x0 0xe00f2000 0x0 0x2000>,
109 <0x0 0xe00f4000 0x0 0x2000>,
110 <0x0 0xe00f6000 0x0 0x2000>;
118 reg = <0x0 0xe0120000 0x0 0x2000>;
126 reg = <0x0 0xe0122000 0x0 0x2000>;
134 reg = <0x0 0xe0124000 0x0 0x2000>;
142 reg = <0x0 0xe0126000 0x0 0x2000>;
150 reg = <0x0 0xe0128000 0x0 0x2000>;
158 reg = <0x0 0xe012a000 0x0 0x2000>;
166 reg = <0x0 0xe012c000 0x0 0x2000>;
H A Ds900.dtsi114 <0x0 0xe00f2000 0x0 0x2000>,
115 <0x0 0xe00f4000 0x0 0x2000>,
116 <0x0 0xe00f6000 0x0 0x2000>;
124 reg = <0x0 0xe0120000 0x0 0x2000>;
132 reg = <0x0 0xe0122000 0x0 0x2000>;
140 reg = <0x0 0xe0124000 0x0 0x2000>;
148 reg = <0x0 0xe0126000 0x0 0x2000>;
156 reg = <0x0 0xe0128000 0x0 0x2000>;
164 reg = <0x0 0xe012a000 0x0 0x2000>;
172 reg = <0x0 0xe012c000 0x0 0x2000>;
[all …]
/linux/arch/arc/boot/dts/
H A Dhaps_hs.dts54 reg = <0xf0000000 0x2000>;
71 reg = <0xf0100000 0x2000>;
77 reg = <0xf0102000 0x2000>;
83 reg = <0xf0104000 0x2000>;
89 reg = <0xf0106000 0x2000>;
95 reg = <0xf0108000 0x2000>;
/linux/drivers/crypto/inside-secure/
H A Dsafexcel.h71 #define EIP197_XLX_IRQ_BLOCK_ID_ADDR 0x2000
167 #define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n)))
168 #define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
169 #define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
170 #define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
171 #define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n)))
172 #define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
173 #define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
174 #define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n)))
175 #define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml133 reg = <0x0 0x2000>,
134 <0x2000 0x2000>,
141 reg = <0x34000 0x2000>,
150 reg = <0x38000 0x2000>,
172 reg = <0x0 0x2000>,
173 <0x2000 0x2000>,
192 reg = <0x4000 0x2000>,
225 reg = <0x6000 0x2000>,
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_opp_csc_v.c79 { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
514 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
516 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
518 {0x2cdd, 0x2000, 0x0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
519 0x0, 0x2000, 0x38b4, 0xe3a6} },
524 {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
525 0x2000, 0x3b61, 0xe24f} },
/linux/Documentation/devicetree/bindings/net/
H A Dcortina,gemini-ethernet.yaml106 <0x60004000 0x2000>, /* V-bit */
107 <0x60006000 0x2000>; /* A-bit */
114 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
115 <0x6000a000 0x2000>; /* Port 0 GMAC */
127 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
128 <0x6000e000 0x2000>; /* Port 1 GMAC */
/linux/drivers/net/ethernet/cirrus/
H A Dcs89x0.h97 #define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
139 #define RX_RUNT_ENBL 0x2000
150 #define RX_RUNT_ACCEPT 0x2000
174 #define TX_RUNT 0x2000
184 #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
194 #define TWO_PART_DEFDIS 0x2000
203 #define HCB1_ENBL 0x2000
212 #define RX_DMA_SIZE_64K 0x2000
231 #define RX_RUNT 0x2000
254 #define RX_MISS_OVRFLW 0x2000
[all …]
/linux/include/linux/mfd/
H A Dwm8400-private.h162 #define WM8400_GPIO2_PU 0x2000 /* GPIO2_PU */
163 #define WM8400_GPIO2_PU_MASK 0x2000 /* GPIO2_PU */
204 #define WM8400_GPIO4_PU 0x2000 /* GPIO4_PU */
205 #define WM8400_GPIO4_PU_MASK 0x2000 /* GPIO4_PU */
246 #define WM8400_GPIO6_PU 0x2000 /* GPIO6_PU */
247 #define WM8400_GPIO6_PU_MASK 0x2000 /* GPIO6_PU */
479 #define WM8400_DC1_SLEEP 0x2000 /* DC1_SLEEP */
480 #define WM8400_DC1_SLEEP_MASK 0x2000 /* DC1_SLEEP */
509 #define WM8400_DC1_FRC_PWM 0x2000 /* DC1_FRC_PWM */
510 #define WM8400_DC1_FRC_PWM_MASK 0x2000 /* DC1_FRC_PWM */
[all …]
/linux/arch/arm64/boot/dts/broadcom/bcmbca/
H A Dbcm63146.dtsi96 <0x2000 0x2000>,
97 <0x4000 0x2000>,
98 <0x6000 0x2000>;
126 reg = <0x1800 0x600>, <0x2000 0x10>;
/linux/include/linux/mfd/wm8350/
H A Daudio.h117 #define WM8350_DAC_MONO 0x2000
156 #define WM8350_DAC_MUTERATE 0x2000
250 #define WM8350_INL_ZC 0x2000
258 #define WM8350_INR_ZC 0x2000
399 #define WM8350_OUT1L_ZC 0x2000
408 #define WM8350_OUT1R_ZC 0x2000
417 #define WM8350_OUT2L_ZC 0x2000
425 #define WM8350_OUT2R_ZC 0x2000
440 #define WM8350_AIF_TRI 0x2000
478 #define WM8350_AIFADC_WR_TST 0x2000
/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h57 #define SPI_FLASH_CTRL_EN_VPD 0x2000
308 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100,
315 #define MII_CR_SPEED_100 0x2000
331 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
344 #define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
357 #define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
373 #define MII_ATLX_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
384 #define MII_ATLX_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
395 #define MII_ATLX_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
438 #define MII_ATLX_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal2.h20 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000
32 #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000
57 #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000
87 #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000
92 #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000
197 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000
270 #define MV88E6352_G2_NOEGR_POLICY 0x2000
271 #define MV88E6390_G2_LAG_ID_4 0x2000
H A Dglobal1.h60 #define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000
79 #define MV88E6XXX_G1_VTU_OP_NOOP 0x2000
92 #define MV88E6390_G1_VTU_VID_PAGE 0x2000
123 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000
214 #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000
233 #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000
236 #define MV88E6085_G1_CTL2_P10RM 0x2000
258 #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000
/linux/Documentation/devicetree/bindings/arm/omap/
H A Dctrl.txt41 reg = <0x2000 0x2000>;
44 ranges = <0 0x2000 0x2000>;

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