| /linux/include/drm/intel/ | 
| H A D | i915_hdcp_interface.h | 20  * @HDCP_PORT_TYPE_LSPCON: HDCP2.2 discrete wired Tx port with LSPCON22  * @HDCP_PORT_TYPE_CPDP: HDCP2.2 discrete wired Tx port using the CPDP (DP 1.3)
 105  * @initiate_hdcp2_session: Initiate a Wired HDCP2.2 Tx Session.
 119  * @close_hdcp_session: Close the Wired HDCP Tx session per port.
 315 /* hdcp_command_id: Enumeration of all WIRED HDCP Command IDs */
 322 	/* The wired HDCP Tx commands */
 373  * Data structures for integrated wired HDCP2 Tx in
 376 /* HECI struct for integrated wired HDCP Tx session initiation. */
 390 /* HECI struct for ending an integrated wired HDCP Tx session. */
 401 /* HECI struct for integrated wired HDCP Tx Rx Cert verification. */
 [all …]
 
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| /linux/arch/mips/include/asm/ | 
| H A D | tlb.h | 16 	unsigned int wired = read_c0_wired();  in num_wired_entries()  local19 		wired &= MIPSR6_WIRED_WIRED;  in num_wired_entries()
 21 	return wired;  in num_wired_entries()
 
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| H A D | mmu_context.h | 78  * The ginvt instruction will invalidate wired entries when its type field80  * allow the kernel to create wired entries with the MMID of current->active_mm
 81  * then those wired entries could be invalidated when we later use ginvt to
 84  * In order to prevent ginvt from trashing wired entries, we reserve one MMID
 85  * for use by the kernel when creating wired entries. This MMID will never be
 
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| H A D | regdef.h | 22 #define GPR_ZERO	0	/* wired zero */65 #define GPR_ZERO	0	/* wired zero */
 112 #define zero	$0	/* wired zero */
 155 #define zero	$0	/* wired zero */
 
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| H A D | tlbmisc.h | 6  * - add_wired_entry() add a fixed TLB entry, and move wired register
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| /linux/Documentation/devicetree/bindings/iommu/ | 
| H A D | riscv,iommu.yaml | 19   Hardware uses in-memory command and fault reporting queues with wired62       Wired interrupt vectors available for RISC-V IOMMU to notify the
 80     /* Example 1 (IOMMU device with wired interrupts) */
 100     /* Example 2 (IOMMU device with shared wired interrupt) */
 
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| /linux/arch/arm/boot/dts/allwinner/ | 
| H A D | sun8i-v3s-anbernic-rg-nano.dts | 183 /* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */191 /* DCDC3 wired into every 3.3v input that isn't the RTC. */
 199 /* LDO1 wired into RTC, voltage is hard-wired at 3.3v. */
 205 /* LDO2 wired into VCC-PLL and audio codec. */
 
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| /linux/arch/sh/mm/ | 
| H A D | tlb-urb.c | 39 	 * Insert this entry into the highest non-wired TLB slot (via  in tlb_wire_entry()62  * Unwire the last wired TLB entry.
 82 	 * have been wired.  in tlb_unwire_entry()
 
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| /linux/Documentation/devicetree/bindings/iio/resolver/ | 
| H A D | adi,ad2s1210.yaml | 44   Note on SPI connections: The CS line on the AD2S1210 should hard-wired to105       RES0 and RES1 pins are hard-wired to match the assigned-resolution-bits
 120       This is used to indicate the selected mode if A0 and A1 are hard-wired
 130       RES1 are hard-wired to match this value.
 
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| /linux/arch/mips/sgi-ip30/ | 
| H A D | ip30-common.h | 7  * Power Switch is wired via BaseIO BRIDGE slot #6.9  * ACFail is wired via BaseIO BRIDGE slot #7.
 
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| /linux/arch/mips/mm/ | 
| H A D | tlb-r3k.c | 223 	static unsigned long wired = 0;  in add_wired_entry()  local225 	if (wired < 8) {  in add_wired_entry()
 235 		write_c0_index(wired);  in add_wired_entry()
 236 		wired++;				/* BARRIER */  in add_wired_entry()
 
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| /linux/Documentation/devicetree/bindings/media/ | 
| H A D | st-rc.txt | 12 	  be present iff the rx pins are wired up.15 	  be present iff the tx pins are wired up.
 
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| /linux/Documentation/devicetree/bindings/spi/ | 
| H A D | spi-peripheral-props.yaml | 93     description: Several SPI memories can be wired in stacked mode.105     description: Several SPI memories can be wired in parallel mode.
 111       many busses as devices must be wired. The size of each chip should
 
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| /linux/arch/mips/kvm/ | 
| H A D | vz.c | 2463 	unsigned int wired = read_gc0_wired();  in kvm_vz_vcpu_save_wired()  local2467 	/* Expand the wired TLB array if necessary */  in kvm_vz_vcpu_save_wired()
 2468 	wired &= MIPSR6_WIRED_WIRED;  in kvm_vz_vcpu_save_wired()
 2469 	if (wired > vcpu->arch.wired_tlb_limit) {  in kvm_vz_vcpu_save_wired()
 2470 		tlbs = krealloc(vcpu->arch.wired_tlb, wired *  in kvm_vz_vcpu_save_wired()
 2474 			wired = vcpu->arch.wired_tlb_limit;  in kvm_vz_vcpu_save_wired()
 2477 			vcpu->arch.wired_tlb_limit = wired;  in kvm_vz_vcpu_save_wired()
 2481 	if (wired)  in kvm_vz_vcpu_save_wired()
 2482 		/* Save wired entries from the guest TLB */  in kvm_vz_vcpu_save_wired()
 2483 		kvm_vz_save_guesttlb(vcpu->arch.wired_tlb, 0, wired);  in kvm_vz_vcpu_save_wired()
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| /linux/drivers/input/joystick/ | 
| H A D | xpad.c | 138 	{ 0x03f0, 0x038D, "HyperX Clutch", 0, XTYPE_XBOX360 },			/* wired */199 	{ 0x0738, 0x4716, "Mad Catz Wired Xbox 360 Controller", 0, XTYPE_XBOX360 },
 204 …{ 0x0738, 0x4738, "Mad Catz Wired Xbox 360 Controller (SFIV)", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX…
 240 	{ 0x0e6f, 0x011f, "Rock Candy Gamepad Wired Controller", 0, XTYPE_XBOX360 },
 242 	{ 0x0e6f, 0x0133, "Xbox 360 Wired Controller", 0, XTYPE_XBOX360 },
 243 	{ 0x0e6f, 0x0139, "Afterglow Prismatic Wired Controller", 0, XTYPE_XBOXONE },
 245 	{ 0x0e6f, 0x0146, "Rock Candy Wired Controller for Xbox One", 0, XTYPE_XBOXONE },
 248 	{ 0x0e6f, 0x015d, "PDP Mirror's Edge Official Wired Controller for Xbox One", 0, XTYPE_XBOXONE },
 254 	{ 0x0e6f, 0x0201, "Pelican PL-3601 'TSZ' Wired Xbox 360 Controller", 0, XTYPE_XBOX360 },
 260 	{ 0x0e6f, 0x02a2, "PDP Wired Controller for Xbox One - Crimson Red", 0, XTYPE_XBOXONE },
 [all …]
 
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| /linux/arch/arm/boot/dts/st/ | 
| H A D | ste-href-tvk1281618-r2.dtsi | 101 				 * the falling edge if they could be wired together.122 				 * the falling edge if they could be wired together.
 159 				 * the falling edge if they could be wired together.
 
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| /linux/Documentation/devicetree/bindings/net/dsa/ | 
| H A D | mediatek,mt7530.yaml | 39       the gmac of the SoC which is wired to port 5 can connect to the PHY.54     - For the multi-chip module MT7530, in case of an external phy wired to
 63     - Port 5 can be wired to an external phy. Port 5 becomes a DSA user port.
 65       For the multi-chip module MT7530, the external phy must be wired TX to TX
 66       to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired
 
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| /linux/Documentation/hwmon/ | 
| H A D | via686a.rst | 80 in which case the sensor inputs will not be wired. This is the case of84 not wired for hardware monitoring.
 
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| H A D | smsc47m192.rst | 57 the motherboard has this input wired to VID4.87 		      would typically be wired to the diode inside the CPU)
 
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| /linux/arch/arm/boot/dts/nxp/imx/ | 
| H A D | imx6ul-tx6ul-mainboard.dts | 177 			/* LCD_DATA08..09 not wired */184 			/* LCD_DATA16..17 not wired */
 
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| /linux/Documentation/scsi/ | 
| H A D | 53c700.rst | 37 driver, you need to know three things about the way the chip is wired45 the SCSI Id from the card bios or whether the chip is wired for
 
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| /linux/Documentation/devicetree/bindings/display/panel/ | 
| H A D | panel-mipi-dbi-spi.yaml | 64   If the panel is wired to the controller at an offset specify this using87       wired up).
 
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| /linux/drivers/usb/core/ | 
| H A D | of.c | 105  * connect_type is "hard-wired". If there isn't an OF graph or child node at140 	 * Hard-wired ports are child nodes with a reg property corresponding  in usb_of_get_connect_type()
 
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| /linux/Documentation/devicetree/bindings/bus/ | 
| H A D | ti-sysc.yaml | 117       Target module reset bit in the RSTCTRL register if wired for the module.125       "rstctrl" if only one reset bit is wired for the module.
 
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| /linux/arch/arm/boot/dts/marvell/ | 
| H A D | armada-385-db-ap.dts | 43 				 * This bus is wired to two EEPROM78 			 * wired to the mini-USB connector
 
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