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Searched full:wclk (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/staging/greybus/
H A Daudio_apbridgea.h13 * - the DSP on the MSM8994 is the clock master for MCLK, BCLK, and WCLK
14 * - WCLK changes on the falling edge of BCLK
15 * - WCLK low for left channel; high for right channel
/linux/sound/soc/amd/
H A Dacp-da7219-max98357a.c76 da7219_dai_wclk = devm_clk_get(component->dev, "da7219-dai-wclk"); in cz_da7219_init()
112 * Set wclk to 48000 because the rate constraint of this driver is in da7219_clk_enable()
158 rt5682_dai_wclk = devm_clk_get(component->dev, "rt5682-dai-wclk"); in cz_rt5682_init()
197 * Set wclk to 48000 because the rate constraint of this driver is in rt5682_clk_enable()
204 dev_err(rtd->dev, "Error setting wclk rate: %d\n", ret); in rt5682_clk_enable()
214 dev_err(rtd->dev, "can't enable wclk %d\n", ret); in rt5682_clk_enable()
/linux/Documentation/devicetree/bindings/media/
H A Dsamsung,exynos4210-csis.yaml92 samsung,csis-wclk:
167 samsung,csis-wclk;
/linux/Documentation/devicetree/bindings/sound/
H A Dti,tlv320adc3xxx.yaml56 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
74 - 7 # ADC3XXX_GPIO_SECONDARY_WCLK - Codec interface secondary WCLK
H A Ddialog,da7219.yaml60 Name given for DAI WCLK and BCLK outputs.
213 clock-output-names = "da7219-dai-wclk", "da7219-dai-bclk";
H A Drealtek,rt5682s.yaml140 clock-output-names = "rt5682-dai-wclk", "rt5682-dai-bclk";
/linux/sound/soc/codecs/
H A Dda7219.c1429 struct clk *wclk = da7219->dai_clks[DA7219_DAI_WCLK_IDX]; in da7219_set_dai_tdm_slot() local
1476 sr = clk_get_rate(wclk); in da7219_set_dai_tdm_slot()
1489 "Failed to set TDM BCLKs per WCLK %d: %d\n", in da7219_set_dai_tdm_slot()
1565 struct clk *wclk = da7219->dai_clks[DA7219_DAI_WCLK_IDX]; in da7219_hw_params() local
1600 if (da7219->master && wclk) { in da7219_hw_params()
1601 ret = clk_set_rate(wclk, sr); in da7219_hw_params()
1604 "Failed to set WCLK SR %lu: %d\n", sr, ret); in da7219_hw_params()
1655 "Failed to set BCLKs per WCLK %d: %d\n", in da7219_hw_params()
1779 pdata->dai_clk_names[DA7219_DAI_WCLK_IDX] = "da7219-dai-wclk"; in da7219_fw_to_pdata()
2088 * derived from multiple parent WCLK rates (BCLK rates are set as a in da7219_bclk_determine_rate()
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H A Drt5682.c2666 * Only accept to set wclk rate to 44.1k or 48kHz. in rt5682_wclk_recalc_rate()
2689 * Only accept to set wclk rate to 44.1k or 48kHz. in rt5682_wclk_determine_rate()
2719 * Whether the wclk's parent clk (mclk) exists or not, please ensure in rt5682_wclk_set_rate()
2720 * it is fixed or set to 48MHz before setting wclk rate. It's a in rt5682_wclk_set_rate()
2728 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", in rt5682_wclk_set_rate()
2810 * BCLK rates are set as a multiplier of WCLK in HW. in rt5682_bclk_determine_rate()
2811 * We don't allow changing the parent WCLK. We just do in rt5682_bclk_determine_rate()
2812 * some rounding down based on the parent WCLK rate in rt5682_bclk_determine_rate()
2879 /* Make MCLK the parent of WCLK */ in rt5682_register_dai_clks()
2887 /* Make WCLK the parent of BCLK */ in rt5682_register_dai_clks()
H A Drt5682s.c38 .dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
2602 * Only accept to set wclk rate to 44.1k or 48kHz. in rt5682s_wclk_recalc_rate()
2625 * Only accept to set wclk rate to 44.1k or 48kHz. in rt5682s_wclk_determine_rate()
2651 * Whether the wclk's parent clk (mclk) exists or not, please ensure in rt5682s_wclk_set_rate()
2652 * it is fixed or set to 48MHz before setting wclk rate. It's a in rt5682s_wclk_set_rate()
2660 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", in rt5682s_wclk_set_rate()
2734 * BCLK rates are set as a multiplier of WCLK in HW. in rt5682s_bclk_determine_rate()
2735 * We don't allow changing the parent WCLK. We just do in rt5682s_bclk_determine_rate()
2736 * some rounding down based on the parent WCLK rate in rt5682s_bclk_determine_rate()
2802 /* Make MCLK the parent of WCLK */ in rt5682s_register_dai_clks()
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H A Dda7213.c1513 /* By default only 64 BCLK per WCLK is supported */ in da7213_set_dai_fmt()
H A Dda7218.c2008 /* By default 64 BCLKs per WCLK is supported */ in da7218_set_dai_fmt()
/linux/include/dt-bindings/sound/
H A Dtlv320adc3xxx.h19 #define ADC3XXX_GPIO_SECONDARY_WCLK 9 /* Codec interface secondary WCLK */
/linux/sound/soc/amd/acp/
H A Dacp-mach-common.c77 clk_set_rate(drvdata->wclk, srate); in acp_clk_enable()
80 return clk_prepare_enable(drvdata->wclk); in acp_clk_enable()
129 drvdata->wclk = clk_get(component->dev, "rt5682-dai-wclk"); in acp_card_rt5682_init()
214 clk_disable_unprepare(drvdata->wclk); in acp_card_shutdown()
371 drvdata->wclk = clk_get(component->dev, "rt5682-dai-wclk"); in acp_card_rt5682s_init()
506 clk_set_rate(drvdata->wclk, srate); in acp_card_rt5682s_hw_params()
H A Dacp-mach.h75 struct clk *wclk; member
/linux/drivers/gpu/ipu-v3/
H A Dipu-dc.c55 #define WCLK 0xc9 macro
125 if (opcode == WCLK) { in dc_write_tmpl()
/linux/arch/arm64/boot/dts/renesas/
H A Dwhite-hawk-ard-audio-da7212.dtso23 * | SSI_WS_V pin13 |<----->| pin3 WCLK |
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-midas.dtsi489 samsung,csis-wclk;
/linux/sound/pci/emu10k1/
H A Demu10k1_main.c879 /* Default WCLK set to 48kHz. */ in snd_emu10k1_emu1010_init()