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/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware
29 - description: For implementations complying for Versal NET.
32 - xlnx,versal-net-firmware
33 - const: xlnx,versal-firmware
51 $ref: /schemas/clock/xlnx,versal-clk.yaml#
52 description: The clock controller is a hardware block of Xilinx versal
96 versal-fpga:
97 $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
157 versal-firmware {
[all …]
/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,versal-fpga.yaml4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
7 title: Xilinx Versal FPGA driver.
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
20 - xlnx,versal-fpga
29 versal_fpga: versal-fpga {
30 compatible = "xlnx,versal-fpga";
/linux/Documentation/devicetree/bindings/clock/
H A Dxlnx,versal-clk.yaml4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
7 title: Xilinx Versal clock controller
13 The clock controller is a hardware block of Xilinx versal clock tree. It
21 - xlnx,versal-clk
25 - xlnx,versal-net-clk
26 - const: xlnx,versal-clk
55 - xlnx,versal-clk
74 - xlnx,versal-net-clk
131 compatible = "xlnx,versal-clk";
H A Dxlnx,clocking-wizard.yaml13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
23 - xlnx,versal-clk-wizard
/linux/Documentation/devicetree/bindings/reset/
H A Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
14 The Zynq UltraScale+ MPSoC and Versal has several different resets.
28 For list of all valid reset indices for Versal
29 <dt-bindings/reset/xlnx-versal-resets.h>
35 - xlnx,versal-reset
36 - xlnx,versal-net-reset
/linux/Documentation/devicetree/bindings/watchdog/
H A Dxlnx,versal-wwdt.yaml4 $id: http://devicetree.org/schemas/watchdog/xlnx,versal-wwdt.yaml#
7 title: Xilinx Versal window watchdog timer controller
13 Versal watchdog intellectual property uses window watchdog mode.
27 - xlnx,versal-wwdt
45 compatible = "xlnx,versal-wwdt";
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dxlnx,versal-ddrmc-edac.yaml4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
20 const: xlnx,versal-ddrmc
51 compatible = "xlnx,versal-ddrmc";
/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml29 - xlnx,versal-8.9a
30 - xlnx,versal-net-emmc
61 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
66 - const: xlnx,versal-net-emmc # Versal Net eMMC PHY
238 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
/linux/Documentation/devicetree/bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.yaml42 - xlnx,versal-ipi-mailbox
89 - xlnx,versal-ipi-dest-mailbox
223 compatible = "xlnx,versal-ipi-mailbox";
235 compatible = "xlnx,versal-ipi-dest-mailbox";
245 compatible = "xlnx,versal-ipi-dest-mailbox";
/linux/drivers/fpga/
H A Dversal-fpga.c57 mgr = devm_fpga_mgr_register(dev, "Xilinx Versal FPGA Manager", in versal_fpga_probe()
63 { .compatible = "xlnx,versal-fpga", },
79 MODULE_DESCRIPTION("Xilinx Versal FPGA Manager");
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml23 - xlnx,versal-r5fss
24 - xlnx,versal-net-r52fss
81 - xlnx,versal-r5f
82 - xlnx,versal-net-r52f
156 - xlnx,versal-net-r52fss
194 - xlnx,versal-r5fss
/linux/Documentation/devicetree/bindings/bus/
H A Dxlnx,versal-net-cdx.yaml4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
39 const: xlnx,versal-net-cdx
73 compatible = "xlnx,versal-net-cdx";
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dxlnx,versal-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/xlnx,versal-pinctrl.yaml#
7 title: Xilinx Versal Pinctrl
17 Versal's pin configuration nodes act as a container for an arbitrary number of
28 const: xlnx,versal-pinctrl
251 compatible = "xlnx,versal-pinctrl";
/linux/Documentation/devicetree/bindings/rtc/
H A Dxlnx,zynqmp-rtc.yaml25 - xlnx,versal-rtc
26 - xlnx,versal-net-rtc
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-zynq.yaml17 - xlnx,versal-gpio-1.0
74 - xlnx,versal-gpio-1.0
/linux/drivers/reset/
H A Dreset-zynqmp.c127 { .compatible = "xlnx,versal-reset", .data = &versal_reset_data, },
128 { .compatible = "xlnx,versal-net-reset", .data = &versal_net_reset_data, },
/linux/Documentation/accel/amdxdna/
H A Damdnpu.rst156 `Versal Adaptive SoC AIE-ML Architecture Manual (AM020)`_ for more details.
280 - `Versal Adaptive SoC AIE-ML Architecture Manual (AM020) <https://docs.amd.com/r/en-US/am020-versa…
/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml30 - xlnx,versal-gem # Xilinx Versal
/linux/drivers/cdx/controller/
H A Dcdx_controller.c3 * CDX host controller driver for AMD versal-net platform.
240 {.compatible = "xlnx,versal-net-cdx",},
H A Dmc_cdx_pcol.h315 * addresses (prior to any potential IOMMU translation). For versal-net, these
629 * interrupt vector. Versal-net implementation specific limitations are that
674 * MSI data to be used by the hardware. On versal-net, only the lower 16-bits
703 * enum: MCDI command directed to versal-net. MCDI responses of this type
H A Dmcdi_functions.h79 * @msi_data: MSI data to be used by the hardware. On versal-net, only the
/linux/drivers/watchdog/
H A Dxilinx_wwdt.c3 * Window watchdog device driver for Xilinx Versal WWDT
236 { .compatible = "xlnx,versal-wwdt", },
/linux/drivers/pci/controller/
H A DKconfig341 bool "Xilinx Versal CPM PCI controller"
346 Xilinx Versal CPM host bridge.
/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-xilinx.yaml18 - xlnx,versal-dwc3
/linux/drivers/edac/
H A Dversal_edac.c3 * Xilinx Versal memory controller driver
133 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PCSR_LOCK-XRAM_SLCR-Register
1042 { .compatible = "xlnx,versal-ddrmc", },

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