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/freebsd/sys/dev/pci/
H A Dpci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
243 #define PCI_QUIRK_DISABLE_FLR 8 /* Function-Level Reset (FLR) not working. */
256 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
257 * or the CMIC-SL (AKA ServerWorks GC_LE).
275 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
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/freebsd/usr.sbin/bhyve/amd64/
H A Dvga.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
120 #define CRTC_OF_VRS9 0x80 /* VRS bit 9 */
124 #define CRTC_OF_VRS8 0x04 /* VRS bit 8 */
131 #define CRTC_CURSOR_START 10
/freebsd/contrib/llvm-project/libunwind/src/
H A DUnwind-EHABI.cpp1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 // Implements ARM zero-cost C++ exceptions
10 //===----------------------------------------------------------------------===//
12 #include "Unwind-EHABI.h"
35 return byteData[(offset & ~(size_t)0x03) + (3 - (offset & (size_t)0x03))]; in getByte()
56 SU16 = 0, // Short descriptor, 16-bit entries
57 LU16 = 1, // Long descriptor, 16-bit entries
58 LU32 = 3, // Long descriptor, 32-bit entries
60 RESERVED4 = 8, RESERVED5 = 9, RESERVED6 = 10, RESERVED7 = 11,
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H A DUnwindRegistersSave.S1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 #define FROM_0_TO_15 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
14 #define FROM_0_TO_31 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,2…
32 # +-----------------------+
34 # +-----------------------+
36 # +-----------------------+ <-- SP
153 sw $10, (4 * 10)($4)
191 sdc1 $f10, (4 * 36 + 8 * 10)($4)
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H A DRegisters.hpp1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
10 //===----------------------------------------------------------------------===//
24 // For emulating 128-bit registers
56 /// Registers_x86 holds the register state of a thread in a 32-bit intel
265 /// Registers_x86_64 holds the register state of a thread in a 64-bit intel
338 uint64_t __padding; // 16-byte align
573 return _xmm[regNum - UNW_X86_64_XMM0]; in getVectorRegister()
583 _xmm[regNum - UNW_X86_64_XMM0] = value; in setVectorRegister()
593 /// Registers_ppc holds the register state of a thread in a 32-bit PowerPC
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/freebsd/contrib/file/magic/Magdir/
H A Dwordprocessors2 #------------------------------------------------------------------------------
17 # /defs/w/wps-works-dos.trid.xml
21 >112 ubeshort =0x0100 Microsoft Works 1-3 (DOS) or 2 (Windows) document
24 !:mime application/vnd-ms-works
25 #!:mime application/x-msworks
35 #!:mime application/x-mspublisher
37 # https://web.archive.org/web/20200930085807/https://reposcope.com/mimetype/application/vnd.ms-publ…
38 !:mime application/vnd.ms-publisher
47 #!:mime application/octet-stream
48 !:mime application/x-cosmi
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/freebsd/sys/contrib/openzfs/cmd/zpool/
H A Dzpool_main.c1 // SPDX-License-Identifier: CDDL-1.0
10 * or https://opensource.org/licenses/CDDL-1.0.
32 * Copyright (c) 2017 Open-E, Inc. All Rights Reserved.
85 static int mount_tp_nthr = 512; /* tpool threads for multi-threaded mounting */
367 * Given a cb->cb_flags with a histogram bit set, return the iostat_type.
371 #define IOS_HISTO_IDX(a) (highbit64(a & IOS_ANYHISTO_M) - 1)
455 return (gettext("\tadd [-afgLnP] [-o property=value] " in get_usage()
458 return (gettext("\tattach [-fsw] [-o property=value] " in get_usage()
459 "<pool> <vdev> <new-device>\n")); in get_usage()
461 return (gettext("\tclear [[--power]|[-nF]] <pool> [device]\n")); in get_usage()
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/freebsd/secure/caroot/trusted/
H A DvTrus_Root_CA.pem27 Public-Key: (4096 bit)
30 70:b4:41:ea:4b:03:5e:10:3f:90:5a:1c:8b:3b:b0:
75 9e:34:fe:e6:1a:64:f6:3a:6b:52:b2:10:78:1a:9f:4c:da:8a:
81 ec:ec:6f:76:ae:91:db:10:8e:04:dc:92:df:a0:f6:e6:ae:49:
94 9b:10:cf:8b:b8:38:5e:5e:c5:b4:a6:02:36:a1:1e:5f:1c:cf:
104 -----BEGIN CERTIFICATE-----
112 AyyNJJrIZIO1aqwTLDPxn9wsYTwaP3BVm60AUn/PBLn+NvqcwBauYv6WTEN+VRS+
134 -----END CERTIFICATE-----
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dvdev_label.c1 // SPDX-License-Identifier: CDDL-1.0
10 * or https://opensource.org/licenses/CDDL-1.0.
31 * ---------------------
57 * ------------------
69 * +------+ +------+ +------+
73 * +------+ +------+ +------+
76 * the same transaction group (10). Each label is mirrored and checksummed, so
94 * is synced. If we add a single device, we do not want to have to re-write
100 * On-disk Format
101 * --------------
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCAsmPrinter.cpp1 //===-- PPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly ------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // of machine-dependent LLVM code to PowerPC assembly language. This printer is
16 //===----------------------------------------------------------------------===//
99 "aix-ssp-tb-bit", cl::init(false),
161 // non-TOC-based local-exec variables.
218 /// PPCLinuxAsmPrinter - PowerPC assembly printer, customized for Linux
252 // This is used for AIX's extra-label-at-definition aliasing strategy.
269 if (MAI->isLittleEndian()) in PPCAIXAsmPrinter()
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H A DPPCISelLowering.h1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
51 /// FSEL - Traditional three-operand fsel node.
55 /// XSMAXC[DQ]P, XSMINC[DQ]P - C-type min/max instructions.
59 /// FCFID - The FCFID instruction, taking an f64 operand and producing
64 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
65 /// unsigned integers and single-precision outputs.
70 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
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H A DPPCISelLowering.cpp1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
106 #define DEBUG_TYPE "ppc-lowering"
108 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
111 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
114 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
117 static cl::opt<bool> DisableSCO("disable-ppc-sco",
120 static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
50 int64_t Value = CE->getValue(); in inRange()
102 // easier for this class to have a register bank (general, floating-point
103 // or access) and a raw register number (0-15). This would postpone the
105 // for context-dependent parsing. However, we do things the current way
108 // Context-dependent parsing can also give us slightly better error
118 // length for D(L,B)-style operands, otherwise it is null.
151 Inst.addOperand(MCOperand::createImm(CE->getValue())); in addExpr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
42 #define DEBUG_TYPE "arm-isel"
46 DisableShifterOp("disable-shifter-op", cl::Hidden,
47 cl::desc("Disable isel of shifter-op"),
50 //===--------------------------------------------------------------------===//
51 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
57 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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