1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
10 //===----------------------------------------------------------------------===//
24 // For emulating 128-bit registers
56 /// Registers_x86 holds the register state of a thread in a 32-bit intel
265 /// Registers_x86_64  holds the register state of a thread in a 64-bit intel
338     uint64_t __padding; // 16-byte align
573   return _xmm[regNum - UNW_X86_64_XMM0];  in getVectorRegister()
583   _xmm[regNum - UNW_X86_64_XMM0] = value;  in setVectorRegister()
593 /// Registers_ppc holds the register state of a thread in a 32-bit PowerPC
994   return _floatRegisters.__fpregs[regNum - UNW_PPC_F0];  in getFloatRegister()
999   _floatRegisters.__fpregs[regNum - UNW_PPC_F0] = value;  in setFloatRegister()
1012   v128 result = _vectorRegisters[regNum - UNW_PPC_V0];  in getVectorRegister()
1018   _vectorRegisters[regNum - UNW_PPC_V0] = value;  in setVectorRegister()
1165 /// Registers_ppc64 holds the register state of a thread in a 64-bit PowerPC
1546   return _vectorScalarRegisters[regNum - UNW_PPC64_F0].asfloat.f;  in getFloatRegister()
1551   _vectorScalarRegisters[regNum - UNW_PPC64_F0].asfloat.f = value;  in setFloatRegister()
1570     return num - UNW_PPC64_VS0;  in getVectorRegNum()
1572     return num - UNW_PPC64_VS32 + 32;  in getVectorRegNum()
1814 /// Registers_arm64  holds the register state of a thread in a 64-bit arm
1855     uint64_t __x[29]; // x0-x28
1865   // Currently only the lower double in 128-bit vectore registers
2087   return _vectorHalfRegisters[regNum - UNW_AARCH64_V0];  in getFloatRegister()
2092   _vectorHalfRegisters[regNum - UNW_AARCH64_V0] = value;  in setFloatRegister()
2109 /// Registers_arm holds the register state of a thread in a 32-bit arm
2167     uint32_t __r[13]; // r0-r12
2198   // Whether D0-D15 are saved in the FTSMX instead of FSTMD format.
2203   // Whether VFP D0-D15 are saved.
2205   // Whether VFPv3 D16-D31 are saved.
2207   // VFP registers D0-D15, + padding if saved using FSTMX
2209   // VFPv3 registers D16-D31, always saved using FSTMD
2259   // Returns true for all non-VFP registers supported by the EHABI  in validRegister()
2260   // virtual register set (VRS).  in validRegister()
2302     return _iwmmx_control[regNum - UNW_ARM_WC0];  in getRegister()
2341     _iwmmx_control[regNum - UNW_ARM_WC0] = value;  in setRegister()
2525   // __unw_get_fpreg can be used to transmit the 64-bit data back.  in validFloatRegister()
2542     return _vfp_d0_d15_pad[regNum - UNW_ARM_D0];  in getFloatRegister()
2550     return _vfp_d16_d31[regNum - UNW_ARM_D16];  in getFloatRegister()
2559     return _iwmmx[regNum - UNW_ARM_WR0];  in getFloatRegister()
2575     _vfp_d0_d15_pad[regNum - UNW_ARM_D0] = value;  in setFloatRegister()
2584     _vfp_d16_d31[regNum - UNW_ARM_D16] = value;  in setFloatRegister()
2594     _iwmmx[regNum - UNW_ARM_WR0] = value;  in setFloatRegister()
2647     unsigned int __r[32]; // r0-r31
2682     return _registers.__r[regNum - UNW_OR1K_R0];  in getRegister()
2697     _registers.__r[regNum - UNW_OR1K_R0] = value;  in setRegister()
2816 /// Registers_mips_o32 holds the register state of a thread in a 32-bit MIPS
2854   /// O32 with 32-bit floating point registers only uses half of this
2855   /// space.  However, using the same layout for 32-bit vs 64-bit
2899     return _registers.__r[regNum - UNW_MIPS_R0];  in getRegister()
2905       p = (uint32_t *)&_floats[regNum - UNW_MIPS_F0];  in getRegister()
2907       p = (uint32_t *)&_floats[(regNum - 1) - UNW_MIPS_F0] + 1;  in getRegister()
2929     _registers.__r[regNum - UNW_MIPS_R0] = value;  in setRegister()
2937       p = (uint32_t *)&_floats[regNum - UNW_MIPS_F0];  in setRegister()
2939       p = (uint32_t *)&_floats[(regNum - 1) - UNW_MIPS_F0] + 1;  in setRegister()
2977   return _floats[regNum - UNW_MIPS_F0];  in getFloatRegister()
2988   _floats[regNum - UNW_MIPS_F0] = value;  in setFloatRegister()
3031     return "$10";  in getRegisterName()
3225     return _registers.__r[regNum - UNW_MIPS_R0];  in getRegister()
3244     _registers.__r[regNum - UNW_MIPS_R0] = value;  in setRegister()
3280   return _floats[regNum - UNW_MIPS_F0];  in getFloatRegister()
3291   _floats[regNum - UNW_MIPS_F0] = value;  in setFloatRegister()
3334     return "$10";  in getRegisterName()
3454 /// Registers_sparc holds the register state of a thread in a 32-bit Sparc
3640 /// Registers_sparc64 holds the register state of a thread in a 64-bit
3664   void setSP(uint64_t value) { _registers.__regs[UNW_SPARC_O6] = value - 2047; }  in setSP()
3723     _registers.__regs[UNW_SPARC_O6] = value - 2047;  in setRegister()
3880     return _registers.__r[regNum - UNW_HEXAGON_R0];  in getRegister()
3893     _registers.__r[regNum - UNW_HEXAGON_R0] = value;  in setRegister()
4008 /// Registers_riscv holds the register state of a thread in a RISC-V
4306   return _floats[regNum - UNW_RISCV_F0];  in getFloatRegister()
4316   _floats[regNum - UNW_RISCV_F0] = value;  in setFloatRegister()
4371     uint64_t __s[64]; // s0-s64
4412     return _registers.__s[regNum - UNW_VE_S0];  in getRegister()
4429     _registers.__s[regNum - UNW_VE_S0] = value;  in setRegister()
4781 /// 64-bit Linux on IBM zSystems process.
4813     double __fpr[16];   // Floating-Point Registers
4847     return _registers.__gpr[regNum - UNW_S390X_R0];  in getRegister()
4863     _registers.__gpr[regNum - UNW_S390X_R0] = value;  in setRegister()
4910     return _registers.__fpr[10];  in getFloatRegister()
4959     _registers.__fpr[10] = value;  in setFloatRegister()
5068 /// Registers_loongarch holds the register state of a thread in a 64-bit
5137     return _registers.__r[regNum - UNW_LOONGARCH_R0];  in getRegister()
5148     _registers.__r[regNum - UNW_LOONGARCH_R0] = value;  in setRegister()
5305   return _floats[regNum - UNW_LOONGARCH_F0];  in getFloatRegister()
5314   _floats[regNum - UNW_LOONGARCH_F0] = value;  in setFloatRegister()