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/freebsd/crypto/openssl/crypto/aes/asm/
H A Dvpaes-loongarch64.pl65 vld $vr2,$t0,0 # iptlo
67 vld $vr5,$a5,0 # round0 key
71 vld $vr0,$t0,16 # ipthi
90 vld $vr1,$t0,-0x40
92 vld $vr4,$t0,0 # Lk_mc_backward[]
128 vld $vr5,$a5,0
133 vld $vr4,$a6, -0x60 # 3 : sbou Lk_sbo
134 vld $vr0,$a6, -0x50 # 0 : sbot Lk_sbo+16
139 vld $vr1,$t0,0x40
159 vld $vr2,$t0,0 # iptlo
[all …]
/freebsd/crypto/openssl/crypto/chacha/asm/
H A Dchacha-loongarch64.pl501 vld @y[0],$t8,0
600 vld @y[0],$inp,16*0
601 vld @y[1],$inp,16*1
602 vld @y[2],$inp,16*2
603 vld @y[3],$inp,16*3
613 vld @y[0],$inp,16*4
614 vld @y[1],$inp,16*5
615 vld @y[2],$inp,16*6
616 vld @y[3],$inp,16*7
626 vld @y[0],$inp,16*8
[all …]
/freebsd/tools/regression/usr.bin/cc/
H A Dfloat.c116 volatile long double vld; in run_tests() local
187 vld = LDBL_EPSILON; in run_tests()
189 1.0F + vf != 1.0F && 1.0 + vd != 1.0 && 1.0L + vld != 1.0L); in run_tests()
249 ld = vld * 0.5; in run_tests()
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dmediatek,iommu.txt40 OVL0 RDMA0 WDMA0 MC PP VLD
50 in each larb. Take a example, There are many ports like MC, PP, VLD in the
H A Dmediatek,iommu.yaml50 OVL0 RDMA0 WDMA0 MC PP VLD
61 in each larb. Take a example, There are many ports like MC, PP, VLD in the
/freebsd/crypto/openssl/crypto/crmf/
H A Dcrmf_lib.c261 OSSL_CRMF_OPTIONALVALIDITY *vld; in OSSL_CRMF_MSG_set0_validity() local
269 if ((vld = OSSL_CRMF_OPTIONALVALIDITY_new()) == NULL) in OSSL_CRMF_MSG_set0_validity()
271 vld->notBefore = notBefore; in OSSL_CRMF_MSG_set0_validity()
272 vld->notAfter = notAfter; in OSSL_CRMF_MSG_set0_validity()
273 tmpl->validity = vld; in OSSL_CRMF_MSG_set0_validity()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td87 // Read the unwritten lanes of the VLD's destination registers.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td114 def : M4UnitL2I<(instregex "VLD")>;
H A DARMISelDAGToDAG.cpp347 // Get the alignment operand for a NEON VLD or VST instruction.
1942 /// of a NEON VLD or VST instruction. The supported values depend on the
2034 // Get the register stride update opcode of a VLD/VST instruction that
2120 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
2137 default: llvm_unreachable("unhandled vld type"); in SelectVLD()
2174 SDNode *VLd; in SelectVLD() local
2200 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops); in SelectVLD()
2230 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops); in SelectVLD()
2235 CurDAG->setNodeMemRefs(cast<MachineSDNode>(VLd), {MemOp}); in SelectVLD()
2238 ReplaceNode(N, VLd); in SelectVLD()
[all …]
H A DARMFixCortexA57AES1742098Pass.cpp176 // VLD Dn, [Rn, #imm] in isSafeAESInput()
H A DARMInstrInfo.td1340 // VLD/VST instructions and checking the alignment is not specified.
1351 // VLD/VST instructions and checking the alignment value.
1362 // VLD/VST instructions and checking the alignment value.
1373 // VLD/VST instructions and checking the alignment value.
1384 // for VLD/VST instructions and checking the alignment value.
1395 // encoding for VLD/VST instructions and checking the alignment value.
1405 // Special version of addrmode6 to handle alignment encoding for VLD-dup
1426 // VLD-dup instruction and checking the alignment is not specified.
1436 // Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup
1447 // Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup
[all …]
H A DARMExpandPseudoInsts.cpp550 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
551 /// operands to real VLD instructions with D register operands.
744 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
765 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); in ExpandLaneOp()
770 assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); in ExpandLaneOp()
H A DARMScheduleM55.td446 def : InstRW<[M55WriteLSE3], (instregex "VLD")>;
H A DARMScheduleA57.td144 "VLD(1|2)LN(d|q)(WB_fixed_|WB_register_)?Asm",
145 "VLD(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm",
H A DARMISelLowering.cpp16017 // to transform to VLD/VST 1_UPD nodes. in TryCombineBaseUpdate()
16385 SDNode *VLD = N->getOperand(0).getNode(); in CombineVLDDUP() local
16386 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) in CombineVLDDUP()
16390 unsigned IntNo = VLD->getConstantOperandVal(1); in CombineVLDDUP()
16406 unsigned VLDLaneNo = VLD->getConstantOperandVal(NumVecs + 3); in CombineVLDDUP()
16407 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
16425 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; in CombineVLDDUP()
16426 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); in CombineVLDDUP()
16427 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, in CombineVLDDUP()
16432 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); in CombineVLDDUP()
[all …]
/freebsd/sys/dev/ocs_fc/
H A Dsli4.h2960 uint32_t vld:1, /** valid */ member
5297 vld:1;
5315 vld:1;
5430 vld:1;
5451 vld:1;
5475 vld:1;
5501 vld:1;
5521 vld:1;
5542 vld:1;
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPInstrPatternsVec.td92 defm : VectorLoad<v256f64, i64, v256i1, "VGT", "VLD">;
93 defm : VectorLoad<v256i64, i64, v256i1, "VGT", "VLD">;
H A DVEInstrVec.td127 // Multiclass for VLD instructions
161 // Section 8.9.1 - VLD (Vector Load)
162 defm VLD : VLDm<"vld", 0x81, V64>;
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp165 Opcode = LoongArch::VLD; in loadRegFromStackSlot()
H A DLoongArchLSXInstrInfo.td1165 def VLD : LSX2RI12_Load<0x2c000000>;
1839 defm : LdPat<load, VLD, vt>;
2208 (VLD GPR:$rj, (to_valid_timm timm:$imm))>;
/freebsd/sys/dev/cxgbe/tom/
H A Dt4_ddp.c1181 uint32_t vld; in do_rx_data_ddp() local
1189 vld = be32toh(cpl->ddpvld); in do_rx_data_ddp()
1190 if (__predict_false(vld & DDP_ERR)) { in do_rx_data_ddp()
1192 __func__, vld, tid, toep); in do_rx_data_ddp()
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_regs.h526 #define BWN_NPHY_VLD_DTSIG BWN_PHY_N(0x159) /* VLD data tones sig */
527 #define BWN_NPHY_VLD_DTDAT BWN_PHY_N(0x15A) /* VLD data tones data */
/freebsd/contrib/ofed/opensm/opensm/
H A Dosm_perfmgr_db.c341 "vld %" PRIu64 " <-- %" PRIu64 " (%" PRIu64 ")\n", in debug_dump_err_reading()
/freebsd/usr.sbin/cxgbetool/
H A Dcxgbetool.c607 printf(" vld:oVLAN"); in parse_val_mask()
610 printf(" vld:VLAN"); in parse_val_mask()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFive7.td558 // VLD*R is LMUL aware

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