| /linux/drivers/clk/versatile/ |
| H A D | clk-icst.c | 3 * Driver for the ICST307 VCO clock found in the ARM Reference designs.
37 * struct clk_icst - ICST VCO clock wrapper
40 * @vcoreg_off: VCO register address
41 * @lockreg_off: VCO lock register address
59 * vco_get() - get ICST VCO settings from a certain ICST
61 * @vco: the VCO struct to return the value in
63 static int vco_get(struct clk_icst *icst, struct icst_vco *vco) in vco_get() argument
81 vco->v = val & INTEGRATOR_AP_CM_BITS; in vco_get()
82 vco->r = 22; in vco_get()
83 vco->s = 1; in vco_get()
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| H A D | icst.c | 27 unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco) in icst_hz() argument
29 u64 dividend = p->ref * 2 * (u64)(vco.v + 8); in icst_hz()
30 u32 divisor = (vco.r + 2) * p->s2div[vco.s]; in icst_hz()
49 struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; in icst_hz_to_vco() local
66 return vco; in icst_hz_to_vco()
68 vco.s = p->idx2s[i]; in icst_hz_to_vco()
91 vco.v = vd - 8; in icst_hz_to_vco()
92 vco.r = rd - 2; in icst_hz_to_vco()
99 return vco; in icst_hz_to_vco()
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| H A D | clk-icst.h | 18 * struct clk_icst_desc - descriptor for the ICST VCO
20 * @vco_offset: offset to the ICST VCO from the provided memory base
21 * @lock_offset: offset to the ICST VCO locking register from the provided
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| H A D | icst.h | 30 unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco);
34 * ICST307 VCO frequency must be between 6MHz and 200MHz (3.3 or 5V).
44 * ICST525 VCO frequency must be between 10MHz and 200MHz (3V) or 320MHz (5V).
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_cdclk.c | 94 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
96 * , where vco is the frequency generated by the PLL; cd2x_div
108 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
111 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
362 unsigned int vco; in intel_hpll_vco() local
382 vco = vco_table[tmp & 0x7]; in intel_hpll_vco()
383 if (vco == 0) in intel_hpll_vco()
384 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
387 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
389 return vco; in intel_hpll_vco()
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| /linux/drivers/clk/berlin/ |
| H A D | berlin2-avpll.c | 19 * VCO with 8 channels each, channel 8 is the odd-one-out and does
26 * Also, here and there the VCO registers are a bit different with
115 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_is_enabled() local
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
127 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_enable() local
130 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
131 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_enable()
135 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
142 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_disable() local
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| /linux/drivers/clk/ |
| H A D | clk-si544.c | 45 /* VCO range is 10.8 .. 12.1 GHz, max depends on speed grade */
203 u64 vco; in si544_calc_muldiv() local
228 vco = FVCO_MIN + ls_freq - 1; in si544_calc_muldiv()
229 do_div(vco, ls_freq); in si544_calc_muldiv()
230 settings->hs_div = vco; in si544_calc_muldiv()
237 /* Calculate VCO frequency (in 10..12GHz range) */ in si544_calc_muldiv()
238 vco = (u64)ls_freq * settings->hs_div; in si544_calc_muldiv()
241 tmp = do_div(vco, FXO); in si544_calc_muldiv()
242 settings->fb_div_int = vco; in si544_calc_muldiv()
245 vco = (u64)tmp << 32; in si544_calc_muldiv()
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| H A D | clk-plldig.c | 33 /* Range of the VCO frequencies, in Hz */
117 * If RFDPHI1 has a value of 1 the VCO frequency is also divided by in plldig_recalc_rate()
256 * The frequency of the VCO cannot be changed during runtime. in plldig_clk_probe()
259 if (!of_property_read_u32(dev->of_node, "fsl,vco-hz", in plldig_clk_probe()
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| /linux/drivers/net/wireless/broadcom/b43/ |
| H A D | radio_2055.h | 72 #define B2055_VCO_CAL1 0x40 /* VCO cal 1 */
73 #define B2055_VCO_CAL2 0x41 /* VCO cal 2 */
74 #define B2055_VCO_CAL3 0x42 /* VCO cal 3 */
75 #define B2055_VCO_CAL4 0x43 /* VCO cal 4 */
76 #define B2055_VCO_CAL5 0x44 /* VCO cal 5 */
77 #define B2055_VCO_CAL6 0x45 /* VCO cal 6 */
78 #define B2055_VCO_CAL7 0x46 /* VCO cal 7 */
79 #define B2055_VCO_CAL8 0x47 /* VCO cal 8 */
80 #define B2055_VCO_CAL9 0x48 /* VCO cal 9 */
81 #define B2055_VCO_CAL10 0x49 /* VCO cal 10 */
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| /linux/drivers/clk/pistachio/ |
| H A D | clk-pll.c | 203 u64 val, vco, old_postdiv1, old_postdiv2; in pll_gf40lp_frac_set_rate() local
213 /* calculate vco */ in pll_gf40lp_frac_set_rate()
214 vco = params->fref; in pll_gf40lp_frac_set_rate()
215 vco *= (params->fbdiv << 24) + params->frac; in pll_gf40lp_frac_set_rate()
216 vco = div64_u64(vco, params->refdiv << 24); in pll_gf40lp_frac_set_rate()
218 if (vco < MIN_VCO_FRAC_FRAC || vco > MAX_VCO_FRAC_FRAC) in pll_gf40lp_frac_set_rate()
219 pr_warn("%s: VCO %llu is out of range %lu..%lu\n", name, vco, in pll_gf40lp_frac_set_rate()
226 if (val > vco / 16) in pll_gf40lp_frac_set_rate()
228 name, val, vco / 16); in pll_gf40lp_frac_set_rate()
360 u32 val, vco, old_postdiv1, old_postdiv2; in pll_gf40lp_laint_set_rate() local
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| /linux/drivers/media/tuners/ |
| H A D | fc0011.c | 21 FC11_REG_VCO, /* VCO */
22 FC11_REG_VCOSEL, /* VCO select */
30 FC11_REG_VCOCAL, /* VCO calibrate */
39 FC11_VCOSEL_2 = 0x08, /* VCO select 2 */
40 FC11_VCOSEL_1 = 0x10, /* VCO select 1 */
51 FC11_VCOCAL_RUN = 0, /* VCO calibration run */
52 FC11_VCOCAL_VALUEMASK = 0x3F, /* VCO calibration value mask */
53 FC11_VCOCAL_OK = 0x40, /* VCO calibration Ok */
54 FC11_VCOCAL_RESET = 0x80, /* VCO calibration reset */
132 /* Initiate VCO calibration */
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| H A D | max2165.c | 224 u8 vco, vco_sub_band, adc; in max2165_debug_status() local
236 vco = autotune >> 6; in max2165_debug_status()
240 dprintk("auto VCO active: %d, auto VCO success: %d\n", in max2165_debug_status()
246 dprintk("VCO: %d, VCO Sub-band: %d, ADC: %d\n", vco, vco_sub_band, adc); in max2165_debug_status()
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| /linux/drivers/video/fbdev/kyro/ |
| H A D | STG4000InitDevice.c | 69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
72 #define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
73 #define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
74 #define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
75 #define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
167 /* Calc VCO at full accuracy */ in ProgramClock()
172 * Check it's within restricted VCO range in ProgramClock()
175 * against VCO limit in ProgramClock()
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | fsl,plldig.yaml | 30 fsl,vco-hz:
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
35 its own desired VCO frequency for the PLL.
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| H A D | arm,syscon-icst.yaml | 74 description: The VCO register
77 description: Parent clock for the ICST VCO
87 vco-offset:
89 description: Offset to the VCO register for the oscillator
105 vco-offset = <0x00>;
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| H A D | qcom,dispcc-sc8280xp.yaml | 31 - description: DisplayPort 0 VCO div clock
33 - description: DisplayPort 1 VCO div clock
35 - description: DisplayPort 2 VCO div clock
37 - description: DisplayPort 3 VCO div clock
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| H A D | qcom,dispcc-sm8x50.yaml | 38 - description: VCO DIV clock from DP PHY
40 - description: VCO DIV clock from eDP PHY
42 - description: VCO DIV clock from DP1 PHY
44 - description: VCO DIV clock from DP2 PHY
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| H A D | ti,lmk04832.yaml | 60 ti,vco-hz:
61 description: Optional to set VCO frequency of the PLL in Hertz.
183 ti,vco-hz = <2457600000>;
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| /linux/drivers/net/wireless/zydas/zd1211rw/ |
| H A D | zd_rf_uw2453.c | 25 * fractional divide ratio) and 3 (VCO config).
29 * of different VCO configurations on channel 1 until we detect a PLL lock.
30 * When this happens, we remember which VCO configuration produced the lock
34 * If we do not see a PLL lock on any standard VCO config, we fall back on an
35 * autocal configuration, which has a fixed (as opposed to per-channel) VCO
39 /* The per-channel synth values for all standard VCO configurations. These get
58 /* This table stores the synthesizer fractional divide ratio for *all* VCO
78 /* Here is the data for all the standard VCO configurations. We shrink our
206 /* The VCO configuration for autocal (all channels) */
235 /* index into synth/VCO config tables where PLL lock was found
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| /linux/drivers/clk/bcm/ |
| H A D | clk-iproc-pll.c | 27 /* number of VCO frequency bands */
115 * Based on the target frequency, find a match from the VCO frequency parameter
277 struct iproc_pll_vco_param *vco) in pll_fractional_change_only() argument
293 if (ndiv_int != vco->ndiv_int) in pll_fractional_change_only()
299 if (pdiv != vco->pdiv) in pll_fractional_change_only()
305 static int pll_set_rate(struct iproc_clk *clk, struct iproc_pll_vco_param *vco, in pll_set_rate() argument
311 unsigned long rate = vco->rate; in pll_set_rate()
321 if (vco->pdiv == 0) in pll_set_rate()
324 ref_freq = parent_rate / vco->pdiv; in pll_set_rate()
326 /* determine Ki and Kp index based on target VCO frequency */ in pll_set_rate()
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| H A D | clk-iproc.h | 62 * auto calculates VCO frequency parameters based on the provided leaf
79 * Parameters for VCO frequency configuration
81 * VCO frequency =
205 const struct iproc_pll_vco_param *vco,
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| /linux/drivers/media/dvb-frontends/ |
| H A D | stb6100.c | 74 [STB6100_VCO] = "VCO",
348 /* PLL Loop disabled, bias on, VCO on, synth on */ in stb6100_set_frequency()
356 /* VCO divide ratio (LO divide ratio, VCO prescaler enable). */ in stb6100_set_frequency()
362 /* VCO enabled, search clock off as per LL3.7, 3.4.1 */ in stb6100_set_frequency()
383 /* F(VCO) = F(LO) * (ODIV == 0 ? 2 : 4) */ in stb6100_set_frequency()
385 /* N(I) = floor(f(VCO) / (f(XTAL) * (PSD2 ? 2 : 1))) */ in stb6100_set_frequency()
387 /* N(F) = round(f(VCO) / f(XTAL) * (PSD2 ? 2 : 1) - N(I)) * 2 ^ 9 */ in stb6100_set_frequency()
450 regs[STB6100_LPEN] = 0xfb; /* PLL Loop enabled, bias on, VCO on, synth on */ in stb6100_set_frequency()
458 regs[STB6100_VCO] &= ~STB6100_VCO_OCK; /* VCO fast search */ in stb6100_set_frequency()
465 regs[STB6100_VCO] &= ~STB6100_VCO_OSCH; /* vco search disabled */ in stb6100_set_frequency()
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | cdv_intel_display.c | 39 .vco = {.min = 1800000, .max = 3600000},
51 .vco = {.min = 1800000, .max = 3600000},
66 .vco = {.min = 1809000, .max = 3564000},
78 .vco = {.min = 1800000, .max = 3600000},
90 .vco = {.min = 1809000, .max = 3564000},
102 .vco = {.min = 1800000, .max = 3600000},
291 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
294 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
297 } else if (clock->vco < 3300000) { in cdv_dpll_set_clock_cdv()
398 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
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| /linux/drivers/clk/spear/ |
| H A D | spear1310_clock.c | 232 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
233 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
234 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
235 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
236 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
237 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
238 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
241 /* vco-pll4 rate configuration table, in ascending order of rates */
243 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
244 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-pll.c | 54 u64 vco; in __mtk_pll_recalc_rate() local
62 vco = (u64)fin * pcw; in __mtk_pll_recalc_rate()
64 if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0))) in __mtk_pll_recalc_rate()
67 vco >>= pcwfbits; in __mtk_pll_recalc_rate()
70 vco++; in __mtk_pll_recalc_rate()
72 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
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