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/linux/drivers/staging/media/sunxi/sun6i-isp/
H A Dsun6i_isp_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2021-2022 Bootlin
20 #define SUN6I_ISP_FE_CFG_EN BIT(0)
21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) argument
25 #define SUN6I_ISP_FE_CTRL_SCAP_EN BIT(0)
26 #define SUN6I_ISP_FE_CTRL_VCAP_EN BIT(1)
27 #define SUN6I_ISP_FE_CTRL_PARA_READY BIT(2)
28 #define SUN6I_ISP_FE_CTRL_LUT_UPDATE BIT(3)
29 #define SUN6I_ISP_FE_CTRL_LENS_UPDATE BIT(4)
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/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
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/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (c) 2013-2016 Jens Kuske <jenskuske@gmail.com>
6 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
18 * * VLD : Variable-Length Decoder
38 #define VE_MODE_PIC_WIDTH_IS_4096 BIT(22)
39 #define VE_MODE_PIC_WIDTH_MORE_2048 BIT(21)
96 #define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y) (24 - 4 * (y) - 8 * (x))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
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/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu2_hw_mpeg2_dec.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <media/v4l2-mem2mem.h>
23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
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H A Dhantro_g1_mpeg2_dec.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <media/v4l2-mem2mem.h>
25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
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H A Drockchip_vpu2_hw_h264_dec.c1 // SPDX-License-Identifier: GPL-2.0
6 * Hertz Wong <hertz.wong@rock-chips.com>
7 * Herman Chen <herman.chen@rock-chips.com>
16 #include <media/v4l2-mem2mem.h>
28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
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/linux/drivers/iio/adc/
H A Dstm32-dfsdm.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
15 * STM32 DFSDM - global register map
18 * ----------------------------------------------------------
20 * ----------------------------------------------------------
22 * ----------------------------------------------------------
24 * ----------------------------------------------------------
26 * ----------------------------------------------------------
28 * ----------------------------------------------------------
30 * ----------------------------------------------------------
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/linux/drivers/net/ethernet/altera/
H A Daltera_msgdmahw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 u32 burst_seq_num; /* bit 31:24 write burst
18 * bit 23:16 read burst
19 * bit 15:0 sequence number
21 u32 stride; /* bit 31:16 write stride
22 * bit 15:0 read stride
29 /* mSGDMA descriptor control field bit definitions
32 #define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
33 #define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
34 #define MSGDMA_DESC_CTL_PARK_READS BIT(10)
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H A Daltera_tse.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
53 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) argument
55 /* MAC Command_Config Register Bit Definitions
57 #define MAC_CMDCFG_TX_ENA BIT(0)
58 #define MAC_CMDCFG_RX_ENA BIT(1)
59 #define MAC_CMDCFG_XON_GEN BIT(2)
60 #define MAC_CMDCFG_ETH_SPEED BIT(3)
61 #define MAC_CMDCFG_PROMIS_EN BIT(4)
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/linux/drivers/media/platform/sunxi/sun6i-csi/
H A Dsun6i_csi_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)
5 * Copyright 2021-2022 Bootlin
17 #define SUN6I_CSI_EN_VER_EN BIT(30)
18 #define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16)) argument
19 #define SUN6I_CSI_EN_SRAM_PWDN BIT(8)
20 #define SUN6I_CSI_EN_PTN_START BIT(4)
21 #define SUN6I_CSI_EN_CLK_CNT_SPL_VSYNC BIT(3)
22 #define SUN6I_CSI_EN_CLK_CNT_EN BIT(2)
23 #define SUN6I_CSI_EN_PTN_GEN_EN BIT(1)
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/linux/drivers/memory/
H A Drenesas-rpc-if-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R-Car RPC Interface Registers Definitions
14 #define RPCIF_CMNCR_MD BIT(31)
34 #define RPCIF_DRCR_SSLN BIT(24)
35 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16) argument
36 #define RPCIF_DRCR_RCF BIT(9)
37 #define RPCIF_DRCR_RBE BIT(8)
38 #define RPCIF_DRCR_SSLE BIT(0)
56 #define RPCIF_DRENR_DME BIT(15)
57 #define RPCIF_DRENR_CDE BIT(14)
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/linux/drivers/media/platform/sunxi/sun8i-di/
H A Dsun8i-di.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-mem2mem.h>
13 #include <media/videobuf2-v4l2.h>
14 #include <media/videobuf2-dma-contig.h>
18 #define DEINTERLACE_NAME "sun8i-di"
21 #define DEINTERLACE_MOD_ENABLE_EN BIT(0)
24 #define DEINTERLACE_FRM_CTRL_REG_READY BIT(0)
25 #define DEINTERLACE_FRM_CTRL_WB_EN BIT(2)
26 #define DEINTERLACE_FRM_CTRL_OUT_CTRL BIT(11)
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/linux/tools/perf/util/arm-spe-decoder/
H A Darm-spe-pkt-decoder.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2017-2018, Arm Ltd.
16 #define ARM_SPE_NEED_MORE_BYTES -1
17 #define ARM_SPE_BAD_PACKET -2
73 #define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0)) argument
74 #define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v) (((v) & GENMASK_ULL(55, 48)) >> 48) argument
76 #define SPE_ADDR_PKT_GET_NS(v) (((v) & BIT_ULL(63)) >> 63) argument
77 #define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61) argument
78 #define SPE_ADDR_PKT_GET_CH(v) (((v) & BIT_ULL(62)) >> 62) argument
79 #define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(59, 56)) >> 56) argument
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/linux/drivers/iio/dac/
H A Dad3552r.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AD3552R Digital <-> Analog converters common header
5 * Copyright 2021-2024 Analog Devices Inc.
15 #define AD3552R_MASK_SOFTWARE_RESET (BIT(7) | BIT(0))
16 #define AD3552R_MASK_ADDR_ASCENSION BIT(5)
17 #define AD3552R_MASK_SDO_ACTIVE BIT(4)
19 #define AD3552R_MASK_SINGLE_INST BIT(7)
20 #define AD3552R_MASK_SHORT_INSTRUCTION BIT(3)
22 #define AD3552R_MASK_DEVICE_STATUS(n) BIT(4 + (n))
40 #define AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE BIT(2)
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/linux/arch/riscv/crypto/
H A Daes-riscv64-zvkned-zvbb-zvkg.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
39 // The generated code of this file depends on the following RISC-V extensions:
40 // - RV64I
41 // - RISC-V Vector ('V') with VLEN >= 128 && VLEN < 2048
42 // - RISC-V Vector AES block cipher extension ('Zvkned')
43 // - RISC-V Vector Bit-manipulation extension ('Zvbb')
44 // - RISC-V Vector GCM/GMAC extension ('Zvkg')
51 #include "aes-macros.S"
64 // v1-v15 contain the AES round keys, but they are used for temporaries before
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/linux/drivers/net/can/esd/
H A Desdacc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2015 - 2016 Thomas Körper, esd electronic system design gmbh
3 * Copyright (C) 2017 - 2023 Stefan Mätje, esd electronics gmbh
32 /* Feature flags are contained in the upper 16 bit of the version
34 * extraction into an extra variable => (xx - 16).
36 #define ACC_OV_REG_FEAT_MASK_CANFD BIT(27 - 16)
37 #define ACC_OV_REG_FEAT_MASK_NEW_PSC BIT(28 - 16)
38 #define ACC_OV_REG_FEAT_MASK_DAR BIT(30 - 16)
40 #define ACC_OV_REG_MODE_MASK_ENDIAN_LITTLE BIT(0)
41 #define ACC_OV_REG_MODE_MASK_BM_ENABLE BIT(1)
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/linux/drivers/net/ethernet/wangxun/txgbe/
H A Dtxgbe_type.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
56 #define TXGBE_MIS_RST_MAC_RST(_i) BIT(20 - (_i) * 3)
58 #define TXGBE_MIS_PRB_CTL_LAN_UP(_i) BIT(1 - (_i))
61 #define TXGBE_SPI_ILDR_STATUS_PERST BIT(0) /* PCIE_PERST is done */
62 #define TXGBE_SPI_ILDR_STATUS_PWRRST BIT(1) /* Power on reset is done */
63 #define TXGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i) BIT((_i) + 9) /* lan soft reset done */
67 #define TXGBE_TS_CTL_EVAL_MD BIT(31)
71 #define TXGBE_MAC_MISC_CTL_LINK_STS_MOD BIT(0)
72 #define TXGBE_MAC_MISC_CTL_LINK_PCS FIELD_PREP(BIT(0), 0)
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/linux/sound/soc/rockchip/
H A Drockchip_sai.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ALSA SoC Audio Layer - Rockchip SAI Controller driver
12 #define SAI_XCR_START_SEL_MASK BIT(23)
13 #define SAI_XCR_START_SEL_CHAINED BIT(23)
15 #define SAI_XCR_EDGE_SHIFT_MASK BIT(22)
16 #define SAI_XCR_EDGE_SHIFT_1 BIT(22)
19 #define SAI_XCR_CSR(x) ((x - 1) << 20)
20 #define SAI_XCR_CSR_V(v) ((((v) & SAI_XCR_CSR_MASK) >> 20) + 1) argument
21 #define SAI_XCR_SJM_MASK BIT(19)
22 #define SAI_XCR_SJM_L BIT(19)
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/linux/fs/xfs/libxfs/
H A Dxfs_bit.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * XFS bit manipulation routines.
14 * masks with n high/low bits set, 64-bit values
18 return (uint64_t)-1 << (64 - (n)); in xfs_mask64hi()
22 return ((uint32_t)1 << (n)) - 1; in xfs_mask32lo()
26 return ((uint64_t)1 << (n)) - 1; in xfs_mask64lo()
29 /* Get high bit set out of 32-bit argument, -1 if none set */
30 static inline int xfs_highbit32(uint32_t v) in xfs_highbit32() argument
32 return fls(v) - 1; in xfs_highbit32()
35 /* Get high bit set out of 64-bit argument, -1 if none set */
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/linux/drivers/ufs/host/
H A Dufs-exynos.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
41 * results in non-functioning UFS.
55 #define TX_LINERESET_N(v) (((v) >> 10) & 0xFF) argument
57 #define TX_LINERESET_P(v) (((v) >> 12) & 0xFF) argument
60 #define TX_OV_SLEEP_CNT(v) (((v) >> 5) & 0x7F) argument
62 #define TX_HIGH_Z_CNT_H(v) (((v) >> 8) & 0xF) argument
64 #define TX_HIGH_Z_CNT_L(v) ((v) & 0xFF) argument
66 #define TX_BASE_NVAL_L(v) ((v) & 0xFF) argument
68 #define TX_BASE_NVAL_H(v) (((v) >> 8) & 0xFF) argument
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/linux/drivers/comedi/drivers/
H A Dicp_multi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
23 * It has 16 single-ended or 8 differential Analogue Input channels with
24 * 12-bit resolution. Ranges : 5V, 10V, +/-5V, +/-10V, 0..20mA and 4..20mA.
28 * There are 4 x 12-bit Analogue Outputs. Ranges : 5V, 10V, +/-5V, +/-10V
30 * 16 x Digital Inputs, 24V
32 * 8 x Digital Outputs, 24V, 1A
34 * 4 x 16-bit counters - not implemented
42 #define ICP_MULTI_ADC_CSR_ST BIT(0) /* Start ADC */
[all …]
H A Ds626.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
24 * Number of extended-capability
36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
40 #define S626_GSEL_BIPOLAR5V 0x00F0 /* S626_LP_GSEL setting 5V bipolar. */
41 #define S626_GSEL_BIPOLAR10V 0x00A0 /* S626_LP_GSEL setting 10V bipolar. */
73 /* Interrupt enable bit in ISR and IER. */
180 * Shut down all MC1-controlled
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/linux/sound/ppc/
H A Dsnd_ps3_reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
66 can be cleared by writing a '1' to the corresponding bit. A new interrupt
73 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
75 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
91 an interrupt to the PU. Each bit of PS3_AUDIO_INTR_EN_0 is ANDed with the
92 corresponding bit in PS3_AUDIO_INTR_0. The resulting bits are OR'd together
96 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
98 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
100 Bit assignments are same as PS3_AUDIO_INTR_0
106 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
[all …]
/linux/arch/powerpc/perf/
H A Disa207-common.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
38 #define EVENT_PMC_SHIFT 16 /* PMC number (1-based) */
42 #define EVENT_COMBINE_SHIFT 11 /* Combine bit */
44 #define EVENT_COMBINE(v) (((v) >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK) argument
45 #define EVENT_MARKED_SHIFT 8 /* Marked bit */
73 #define p9_EVENT_COMBINE_SHIFT 10 /* Combine bit */
75 #define p9_EVENT_COMBINE(v) (((v) >> p9_EVENT_COMBINE_SHIFT) & p9_EVENT_COMBINE_MASK) argument
78 #define p9_SDAR_MODE(v) (((v) >> p9_SDAR_MODE_SHIFT) & p9_SDAR_MODE_MASK) argument
95 #define p10_SDAR_MODE(v) (((v) >> p10_SDAR_MODE_SHIFT) & \ argument
108 /* Event Threshold Compare bit constant for power10 in config1 attribute */
[all …]
/linux/drivers/net/phy/
H A Dbcm54140.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include "bcm-phy-lib.h"
16 /* RDB per-port registers
20 #define BCM54140_RDB_INT_LINK BIT(1) /* link status changed */
21 #define BCM54140_RDB_INT_SPEED BIT(2) /* link speed change */
22 #define BCM54140_RDB_INT_DUPLEX BIT(3) /* duplex mode changed */
24 #define BCM54140_RDB_SPARE1_LSLM BIT(2) /* link speed LED mode */
26 #define BCM54140_RDB_SPARE2_WS_RTRY_DIS BIT(8) /* wirespeed retry disable */
29 #define BCM54140_RDB_SPARE3_BIT0 BIT(0)
31 #define BCM54140_RDB_LED_CTRL_ACTLINK0 BIT(4)
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