| /linux/tools/perf/pmu-events/arch/arm64/ |
| H A D | recommended.json | 69 "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
75 "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
123 "PublicDescription": "Attributable Level 2 data or unified TLB refill, read",
129 "PublicDescription": "Attributable Level 2 data or unified TLB refill, write",
135 "PublicDescription": "Attributable Level 2 data or unified TLB access, read",
141 "PublicDescription": "Attributable Level 2 data or unified TLB access, write",
411 "PublicDescription": "Attributable Level 3 data or unified cache access, read",
414 "BriefDescription": "Attributable Level 3 data or unified cache access, read"
417 "PublicDescription": "Attributable Level 3 data or unified cache access, write",
420 "BriefDescription": "Attributable Level 3 data or unified cache access, write"
[all …]
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| H A D | common-and-microarch.json | 219 "PublicDescription": "Attributable Level 1 data or unified TLB access",
222 "BriefDescription": "Attributable Level 1 data or unified TLB access"
261 "PublicDescription": "Attributable Level 2 data or unified TLB access",
264 "BriefDescription": "Attributable Level 2 data or unified TLB access"
309 …itional latency because it returns data from outside the Level 1 data or unified cache of this pro…
393 …unified cache of this processing element. The event indicates to software that the access missed …
399 …unified cache of this processing element. The event indicates to software that the access missed …
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | l2_cache.json | 4 …"PublicDescription": "Counts level 2 cache accesses. level 2 cache is a unified cache for data and…
8 …": "Counts cache line refills into the level 2 cache. level 2 cache is a unified cache for data an…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …evel 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data an…
28 …due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache for data an…
32 …ue to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache for data an…
48 …"PublicDescription": "Counts cache line refills into the level 2 unified cache from any memory rea…
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| H A D | metrics.json | 156 …unified cache that stores both data and instruction. Note that cache accesses in this cache are ei…
163 …unified cache accesses missed per thousand instructions executed. Note that cache accesses in this…
170 …"This metric measures the ratio of level 2 unified TLB accesses missed to the total number of leve…
177 …"BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per th…
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/ |
| H A D | l2_cache.json | 4 …"PublicDescription": "Counts level 2 cache accesses. level 2 cache is a unified cache for data and…
8 …": "Counts cache line refills into the level 2 cache. level 2 cache is a unified cache for data an…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …evel 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data an…
28 …due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache for data an…
32 …ue to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache for data an…
48 …"PublicDescription": "Counts cache line refills into the level 2 unified cache from any memory rea…
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| H A D | metrics.json | 157 …unified cache that stores both data and instruction. Note that cache accesses in this cache are ei…
164 …unified cache accesses missed per thousand instructions executed. Note that cache accesses in this…
171 …"This metric measures the ratio of level 2 unified TLB accesses missed to the total number of leve…
178 …"BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per th…
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | l2_cache.json | 4 …"PublicDescription": "Counts level 2 cache accesses. level 2 cache is a unified cache for data and…
8 …": "Counts cache line refills into the level 2 cache. level 2 cache is a unified cache for data an…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …evel 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data an…
28 …due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache for data an…
32 …ue to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache for data an…
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| H A D | metrics.json | 145 …unified cache that stores both data and instruction. Note that cache accesses in this cache are ei…
152 …unified cache accesses missed per thousand instructions executed. Note that cache accesses in this…
159 …"This metric measures the ratio of level 2 unified TLB accesses missed to the total number of leve…
166 …"BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per th…
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| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/ |
| H A D | cache.json | 107 "PublicDescription": "Level 1 data or unified cache demand access",
110 "BriefDescription": "Level 1 data or unified cache demand access"
113 "PublicDescription": "Level 1 data or unified cache preload or prefetch",
116 "BriefDescription": "Level 1 data or unified cache preload or prefetch"
119 "PublicDescription": "Level 1 data or unified cache refill, preload or prefetch",
122 "BriefDescription": "Level 1 data or unified cache refill, preload or prefetch"
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| /linux/Documentation/devicetree/bindings/cpufreq/ |
| H A D | cpufreq-qcom-hw.yaml | 231 cache-unified;
236 cache-unified;
252 cache-unified;
268 cache-unified;
284 cache-unified;
300 cache-unified;
316 cache-unified;
332 cache-unified;
348 cache-unified;
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| /linux/arch/arm/include/asm/ |
| H A D | unified.h | 3 * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
12 .syntax unified
14 __asm__(".syntax unified");
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| /linux/Documentation/devicetree/bindings/cache/ |
| H A D | socionext,uniphier-system-cache.yaml | 35 cache-unified: true
58 - cache-unified
71 cache-unified;
84 cache-unified;
96 cache-unified;
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| H A D | andestech,ax45mp-cache.yaml | 52 cache-unified: true
66 - cache-unified
80 cache-unified;
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| /linux/drivers/accel/habanalabs/common/ |
| H A D | memory_mgr.c | 14 * @mmg: parent unified memory manager
106 * @mmg: parent unified memory manager
139 * @mmg: parent unified memory manager
224 * @mmg: unified memory manager
307 * hl_mem_mgr_init - initialize unified memory manager
312 * Initialize an instance of unified memory manager
348 * hl_mem_mgr_fini - release unified memory manager
350 * @mmg: parent unified memory manager
353 * Release the unified memory manager. Shall be called from an interrupt context.
381 * @mmg: parent unified memory manager
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| /linux/tools/perf/pmu-events/arch/s390/cf_z10/ |
| H A D | basic.json | 21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
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| /linux/tools/perf/pmu-events/arch/s390/cf_z196/ |
| H A D | basic.json | 21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
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| /linux/tools/perf/pmu-events/arch/s390/cf_z13/ |
| H A D | basic.json | 21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
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| /linux/tools/perf/pmu-events/arch/s390/cf_zec12/ |
| H A D | basic.json | 21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
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| /linux/arch/arm64/boot/dts/amd/ |
| H A D | amd-seattle-cpus.dtsi | 169 cache-unified;
177 cache-unified;
185 cache-unified;
193 cache-unified;
202 cache-unified;
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| H A D | elba-16core.dtsi | 76 cache-unified;
115 cache-unified;
154 cache-unified;
193 cache-unified;
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| /linux/arch/m68k/include/asm/ |
| H A D | m53xxacr.h | 17 * cache setup. They have a unified instruction and data cache, with
56 #define CACHE_SIZE 0x2000 /* 8k of unified cache */
60 #define CACHE_SIZE 0x4000 /* 16k of unified cache */
87 * Unified cache means we will never need to flush for coherency of
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-ls2088a.dtsi | 106 cache-unified;
112 cache-unified;
118 cache-unified;
124 cache-unified;
|
| H A D | fsl-ls2080a.dtsi | 106 cache-unified;
112 cache-unified;
118 cache-unified;
124 cache-unified;
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| /linux/arch/arm/mm/ |
| H A D | cache-v6.S | 187 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
215 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
222 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
228 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
248 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
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| /linux/arch/arm/kernel/ |
| H A D | head-nommu.S | 222 /* Setup a single MPU region, either D or I side (D-side for unified) */
280 /* Determine whether the D/I-side memory map is unified. We set the
286 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
296 beq 1f @ Memory-map not unified
309 beq 2f @ Memory-map not unified
328 beq 3f @ Memory-map not unified
472 /* Determine whether the D/I-side memory map is unified. We set the
484 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
|