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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dxilinx-xadc.txt4 as the UltraScale/UltraScale+ System Monitor.
14 The Xilinx System Monitor is an ADC that is found in the UltraScale and
15 UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
29 UltraScale and UltraScale+ System Monitor.
H A Dxlnx,zynqmp-ams.yaml7 title: Xilinx Zynq Ultrascale AMS controller
/linux/arch/microblaze/kernel/cpu/
H A Dcpuinfo.c79 {"UltraScale Virtex", 0x13},
80 {"UltraScale Kintex", 0x14},
81 {"UltraScale+ Zynq", 0x15},
82 {"UltraScale+ Virtex", 0x16},
83 {"UltraScale+ Kintex", 0x17},
/linux/Documentation/devicetree/bindings/reset/
H A Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
14 The Zynq UltraScale+ MPSoC and Versal has several different resets.
25 For list of all valid reset indices for Zynq UltraScale+ MPSoC
/linux/drivers/clk/zynqmp/
H A DKconfig4 bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
8 Support for the Zynqmp Ultrascale clock controller.
H A DMakefile2 # Zynq Ultrascale+ MPSoC clock specific Makefile
H A Dclk-gate-zynqmp.c3 * Zynq UltraScale+ MPSoC clock controller
H A Dclk-mux-zynqmp.c3 * Zynq UltraScale+ MPSoC mux
H A Dclkc.c3 * Zynq UltraScale+ MPSoC clock controller
675 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n", in zynqmp_register_clocks()
H A Ddivider.c3 * Zynq UltraScale+ MPSoC Divider support
H A Dpll.c3 * Zynq UltraScale+ MPSoC PLL driver
/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,zynqmp-pcap-fpga.yaml7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
/linux/Documentation/devicetree/bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
40 Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
41 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
/linux/Documentation/misc-devices/
H A Dxilinx_sdfec.rst10 This driver supports SD-FEC Integrated Block for Zynq |Ultrascale+ (TM)| RFSoCs.
12 .. |Ultrascale+ (TM)| unicode:: Ultrascale+ U+2122
/linux/Documentation/devicetree/bindings/nvmem/
H A Dxlnx,zynqmp-nvmem.yaml7 title: Zynq UltraScale+ MPSoC Non Volatile Memory interface
/linux/drivers/iio/adc/
H A DKconfig1662 UltraScale/UltraScale+ System Management Wizard.
1669 UltraScale and UltraScale+ FPGAs.
1679 Say yes here to have support for the Xilinx AMS for Ultrascale/Ultrascale+
1683 The driver supports Voltage and Temperature monitoring on Xilinx Ultrascale
H A Dxilinx-xadc-core.c101 /* UltraScale */
587 * Values below are for UltraScale+ (SYSMONE4) using internal reference.
588 * See https://docs.xilinx.com/v/u/en-US/ug580-ultrascale-sysmon
776 * UltraScale, but as per reality setting the power-down bit for the in xadc_power_adc_b()
802 /* UltraScale has only one ADC and supports only continuous mode */ in xadc_get_seq_mode()
1133 /* UltraScale */
/linux/Documentation/devicetree/bindings/rtc/
H A Dxlnx,zynqmp-rtc.yaml7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-zynqmp-fpga9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
/linux/Documentation/devicetree/bindings/soc/xilinx/
H A Dxilinx.yaml13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
/linux/Documentation/devicetree/bindings/mailbox/
H A Dxlnx,zynqmp-ipi-mailbox.yaml11 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
/linux/drivers/rtc/
H A Drtc-zynqmp.c3 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
/linux/drivers/mtd/nand/raw/
H A DKconfig414 Zynq Ultrascale+ MPSoC.

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