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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-utmi.c9 * Marvell A3700 UTMI PHY driver
21 /* Armada 3700 UTMI PHY registers */
62 * - The UTMI PHY wired to the USB3/USB2 controller (otg)
63 * - The UTMI PHY wired to the USB2 controller (host only)
88 struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy); in mvebu_a3700_utmi_phy_power_on() local
90 int usb32 = utmi->caps->usb32; in mvebu_a3700_utmi_phy_power_on()
98 reg = readl(utmi->regs + USB2_PHY_PLL_CTRL_REG0); in mvebu_a3700_utmi_phy_power_on()
102 writel(reg, utmi->regs + USB2_PHY_PLL_CTRL_REG0); in mvebu_a3700_utmi_phy_power_on()
105 regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32), in mvebu_a3700_utmi_phy_power_on()
111 reg = readl(utmi->regs + USB2_PHY_OTG_CTRL); in mvebu_a3700_utmi_phy_power_on()
[all …]
H A DKconfig40 tristate "Marvell A3700 UTMI driver"
46 Enable this to support Marvell A3700 UTMI PHY driver.
71 tristate "Marvell CP110 UTMI driver"
76 Enable this to support Marvell CP110 UTMI PHY driver.
H A DMakefile8 obj-$(CONFIG_PHY_MVEBU_A3700_UTMI) += phy-mvebu-a3700-utmi.o
11 obj-$(CONFIG_PHY_MVEBU_CP110_UTMI) += phy-mvebu-cp110-utmi.o
/linux/drivers/clk/at91/
H A Dclk-utmi.c43 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_prepare() local
52 * the utmi clock. in clk_utmi_prepare()
79 if (utmi->regmap_sfr) { in clk_utmi_prepare()
80 regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM, in clk_utmi_prepare()
87 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr); in clk_utmi_prepare()
89 while (!clk_utmi_ready(utmi->regmap_pmc)) in clk_utmi_prepare()
97 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_is_prepared() local
99 return clk_utmi_ready(utmi->regmap_pmc); in clk_utmi_is_prepared()
104 struct clk_utmi *utmi = to_clk_utmi(hw); in clk_utmi_unprepare() local
106 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, in clk_utmi_unprepare()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmarvell,armada-cp110-utmi-phy.yaml5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
8 title: Marvell Armada CP110/CP115 UTMI PHY
15 Each of two exiting UTMI PHYs could be connected to either USB host or USB device
17 The USB device controller can only be connected to a single UTMI PHY port
19 UTMI PHY0 --------/
23 UTMI PHY1 --------\
28 const: marvell,cp110-utmi-phy
56 Each UTMI PHY port must be represented as a sub-node.
83 cp0_utmi: utmi@580000 {
84 compatible = "marvell,cp110-utmi-phy";
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H A Dnvidia,tegra20-usb-phy.yaml50 - description: UTMI pads control registers clock
55 - description: UTMI timeout clock
56 - description: UTMI pads control registers clock
72 - const: utmi-pads
78 - const: utmi-pads
90 - description: UTMI pads reset
98 - const: utmi-pads
105 enum: [utmi, ulpi, hsic]
128 nvidia,has-utmi-pad-registers:
130 Indicates whether this controller contains the UTMI pad control
[all …]
H A Dmarvell,armada-3700-utmi-phy.yaml5 $id: http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#
8 title: Marvell Armada UTMI/UTMI+ PHY
17 a slightly different UTMI PHY.
22 - marvell,a3700-utmi-host-phy
23 - marvell,a3700-utmi-otg-phy
48 compatible = "marvell,a3700-utmi-host-phy";
H A Dphy-stm32-usbphyc.yaml11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
12 switch. It controls PHY configuration and status, and the UTMI+ switch that
24 |_ UTMI switch_______| OTG controller
216 The value is used to select UTMI switch output.
/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
46 * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
/linux/Documentation/devicetree/bindings/usb/
H A Dusb.yaml38 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
44 enum: [utmi, utmi_wide, ulpi, serial, hsic]
H A Datmel-usb.txt37 - clocks: Should reference the peripheral and the UTMI clocks
40 "usb_clk" for the UTMI clock
44 "utmi", or "hsic".
50 clocks = <&utmi>, <&uhphs_clk>;
122 clocks = <&utmi>, <&udphs_clk>;
H A Domap-usb.txt13 specifying ULPI and UTMI respectively.
55 - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
77 utmi-mode = <2>;
H A Dhisilicon,histb-xhci.txt13 "utmi": for utmi clock
40 clock-names = "bus", "utmi", "pipe", "suspend";
H A Dhisilicon,hi3798mv200-dwc3.yaml31 - description: Controller utmi clock
41 - const: utmi
82 clock-names = "bus", "suspend", "ref", "gm", "gs", "utmi", "pipe";
H A Drockchip,dwc3.yaml64 Controller grf clock OR UTMI clock
76 - utmi
159 - const: utmi
H A Dstarfive,jh7110-usb.yaml43 - description: UTMI APB clock
58 - description: UTMI APB clock reset
/linux/drivers/media/usb/dvb-usb-v2/
H A Drtl28xxu.h197 #define USB_VDRCTRL 0x2F10 /* UTMI vendor signal control */
198 #define USB_VSTAIN 0x2F14 /* UTMI vendor signal status in */
199 #define USB_VLOADM 0x2F18 /* UTMI load vendor signal status in */
200 #define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */
201 #define USB_UTMI_TST 0x2F80 /* UTMI test */
202 #define USB_UTMI_STATUS 0x2F84 /* UTMI status */
/linux/drivers/phy/nuvoton/
H A Dphy-ma35d1-usb2.c22 #define PHY0DEVCKSTB BIT(10) /* PHY 60 MHz UTMI clock stable bit */
46 * make sure USB PHY 60 MHz UTMI Interface Clock ready in ma35_usb_phy_power_on()
56 * wait until USB PHY0 60 MHz UTMI Interface Clock ready in ma35_usb_phy_power_on()
64 /* make sure USB PHY 60 MHz UTMI Interface Clock ready */ in ma35_usb_phy_power_on()
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-db.dts163 phy-names = "utmi";
178 phy-names = "usb", "utmi";
322 phy-names = "utmi";
330 phy-names = "utmi";
/linux/include/soc/at91/
H A Datmel-sfr.h18 #define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */
19 #define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */
/linux/drivers/usb/phy/
H A Dphy-tegra-usb.c269 "Failed to enable UTMI-pads clock: %d\n", ret); in utmip_pad_open()
278 "Failed to initialize UTMI-pads reset: %d\n", ret); in utmip_pad_open()
285 "Failed to assert UTMI-pads reset: %d\n", ret); in utmip_pad_open()
294 "Failed to deassert UTMI-pads reset: %d\n", ret); in utmip_pad_open()
310 "Failed to enable UTMI-pads clock: %d\n", ret); in utmip_pad_close()
317 "Failed to assert UTMI-pads reset: %d\n", ret); in utmip_pad_close()
1083 "Failed to read USB UTMI parameter %s: %d\n", in read_utmi_param()
1102 dev_err(&pdev->dev, "Failed to get UTMI pad regs\n"); in utmi_phy_probe()
1107 * Note that UTMI pad registers are shared by all PHYs, therefore in utmi_phy_probe()
1113 dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n"); in utmi_phy_probe()
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi1003 phy_type = "utmi";
1017 phy_type = "utmi";
1021 clock-names = "reg", "pll_u", "utmi-pads";
1023 reset-names = "usb", "utmi-pads";
1035 nvidia,has-utmi-pad-registers;
1044 phy_type = "utmi";
1058 phy_type = "utmi";
1062 clock-names = "reg", "pll_u", "utmi-pads";
1064 reset-names = "usb", "utmi-pads";
1084 phy_type = "utmi";
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi1176 phy_type = "utmi";
1189 phy_type = "utmi";
1193 clock-names = "reg", "pll_u", "utmi-pads";
1195 reset-names = "usb", "utmi-pads";
1207 nvidia,has-utmi-pad-registers;
1216 phy_type = "utmi";
1229 phy_type = "utmi";
1233 clock-names = "reg", "pll_u", "utmi-pads";
1235 reset-names = "usb", "utmi-pads";
1255 phy_type = "utmi";
[all …]
H A Dtegra30.dtsi1134 phy_type = "utmi";
1150 phy_type = "utmi";
1154 clock-names = "reg", "pll_u", "utmi-pads";
1156 reset-names = "usb", "utmi-pads";
1169 nvidia,has-utmi-pad-registers;
1178 phy_type = "utmi";
1193 phy_type = "utmi";
1197 clock-names = "reg", "pll_u", "utmi-pads";
1199 reset-names = "usb", "utmi-pads";
1220 phy_type = "utmi";
[all …]
H A Dtegra20.dtsi868 phy_type = "utmi";
884 phy_type = "utmi";
889 clock-names = "reg", "pll_u", "timer", "utmi-pads";
891 reset-names = "usb", "utmi-pads";
901 nvidia,has-utmi-pad-registers;
930 reset-names = "usb", "utmi-pads";
940 phy_type = "utmi";
955 phy_type = "utmi";
960 clock-names = "reg", "pll_u", "timer", "utmi-pads";
962 reset-names = "usb", "utmi-pads";

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