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/linux/sound/drivers/
H A Dserial-u16550.c157 static inline void snd_uart16550_add_timer(struct snd_uart16550 *uart) in snd_uart16550_add_timer() argument
159 if (!uart->timer_running) { in snd_uart16550_add_timer()
161 mod_timer(&uart->buffer_timer, jiffies + (HZ + 255) / 256); in snd_uart16550_add_timer()
162 uart->timer_running = 1; in snd_uart16550_add_timer()
166 static inline void snd_uart16550_del_timer(struct snd_uart16550 *uart) in snd_uart16550_del_timer() argument
168 if (uart->timer_running) { in snd_uart16550_del_timer()
169 del_timer(&uart->buffer_timer); in snd_uart16550_del_timer()
170 uart->timer_running = 0; in snd_uart16550_del_timer()
175 static inline void snd_uart16550_buffer_output(struct snd_uart16550 *uart) in snd_uart16550_buffer_output() argument
177 unsigned short buff_out = uart in snd_uart16550_buffer_output()
192 snd_uart16550_io_loop(struct snd_uart16550 * uart) snd_uart16550_io_loop() argument
281 struct snd_uart16550 *uart; snd_uart16550_interrupt() local
300 struct snd_uart16550 *uart; snd_uart16550_buffer_timer() local
314 snd_uart16550_detect(struct snd_uart16550 * uart) snd_uart16550_detect() argument
356 snd_uart16550_do_open(struct snd_uart16550 * uart) snd_uart16550_do_open() argument
448 snd_uart16550_do_close(struct snd_uart16550 * uart) snd_uart16550_do_close() argument
502 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_input_open() local
516 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_input_close() local
531 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_input_trigger() local
544 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_output_open() local
558 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_output_close() local
569 snd_uart16550_buffer_can_write(struct snd_uart16550 * uart,int Num) snd_uart16550_buffer_can_write() argument
578 snd_uart16550_write_buffer(struct snd_uart16550 * uart,unsigned char byte) snd_uart16550_write_buffer() argument
595 snd_uart16550_output_byte(struct snd_uart16550 * uart,struct snd_rawmidi_substream * substream,unsigned char midi_byte) snd_uart16550_output_byte() argument
636 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_output_write() local
727 struct snd_uart16550 *uart = substream->rmidi->private_data; snd_uart16550_output_trigger() local
762 struct snd_uart16550 *uart; snd_uart16550_create() local
832 snd_uart16550_rmidi(struct snd_uart16550 * uart,int device,int outs,int ins,struct snd_rawmidi ** rmidi) snd_uart16550_rmidi() argument
862 struct snd_uart16550 *uart; snd_serial_probe() local
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/linux/Documentation/devicetree/bindings/serial/
H A Dmvebu-uart.txt1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
18 for standard variant of UART and UART2-clk for extended variant
19 of UART. TBG clock (with UART TBG divisors d1=d2=1) or xtal clock
23 (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
24 respectively the UART sum interrupt, the UART TX interrupt and
[all …]
H A Dfsl-imx-uart.yaml4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
19 - fsl,imx25-uart
20 - fsl,imx27-uart
21 - fsl,imx31-uart
22 - fsl,imx35-uart
23 - fsl,imx50-uart
24 - fsl,imx51-uart
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H A Dsnps-dw-apb-uart.yaml4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
7 title: Synopsys DesignWare ABP UART
20 const: starfive,jh7110-uart
35 - renesas,r9a06g032-uart
36 - renesas,r9a06g033-uart
37 - const: renesas,rzn1-uart
40 - rockchip,px30-uart
41 - rockchip,rk1808-uart
42 - rockchip,rk3036-uart
43 - rockchip,rk3066-uart
[all …]
H A D8250.yaml7 title: UART (Universal Asynchronous Receiver/Transmitter)
30 const: mrvl,mmp-uart
62 - const: intel,xscale-uart
63 - const: mrvl,pxa-uart
64 - const: nuvoton,wpcm450-uart
65 - const: nuvoton,npcm750-uart
66 - const: nvidia,tegra20-uart
67 - const: nxp,lpc3220-uart
82 - nxp,lpc1850-uart
84 - ti,da830-uart
[all …]
H A Dsprd-uart.yaml5 $id: http://devicetree.org/schemas/serial/sprd-uart.yaml#
8 title: Spreadtrum serial UART
20 - sprd,sc9860-uart
21 - sprd,sc9863a-uart
22 - sprd,ums512-uart
23 - sprd,ums9620-uart
24 - const: sprd,sc9836-uart
25 - const: sprd,sc9836-uart
39 "enable" for UART module enable clock, "uart" for UART clock, "source"
40 for UART source (parent) clock.
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H A Dbrcm,bcm7271-uart.yaml4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
32 description: The UART register block and optionally the DMA register blocks.
35 - const: uart
37 - const: uart
54 description: The UART interrupt and optionally the DMA interrupt.
57 - const: uart
74 compatible = "brcm,bcm7271-uart";
[all …]
H A Dingenic,uart.yaml4 $id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
7 title: Ingenic SoCs UART controller
22 - ingenic,jz4740-uart
23 - ingenic,jz4750-uart
24 - ingenic,jz4760-uart
25 - ingenic,jz4780-uart
26 - ingenic,x1000-uart
29 - ingenic,jz4770-uart
30 - ingenic,jz4775-uart
31 - const: ingenic,jz4760-uart
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H A Dsifive-serial.yaml7 title: SiFive asynchronous serial interface (UART)
21 - sifive,fu540-c000-uart
22 - sifive,fu740-c000-uart
27 Should be something similar to "sifive,<chip>-uart"
28 for the UART as integrated on a particular chip,
29 and "sifive,uart<version>" for the general UART IP
32 UART HDL that corresponds to the IP block version
35 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
58 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
H A Drenesas,em-uart.yaml4 $id: http://devicetree.org/schemas/serial/renesas,em-uart.yaml#
7 title: Renesas EMMA Mobile UART Interface
17 - renesas,r9a09g011-uart # RZ/V2M
18 - const: renesas,em-uart # generic EMMA Mobile compatible UART
21 - const: renesas,em-uart # generic EMMA Mobile compatible UART
32 - description: UART functional clock
55 const: renesas,r9a09g011-uart
69 compatible = "renesas,em-uart";
/linux/include/uapi/linux/
H A Dserial_core.h19 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
20 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
21 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
22 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
23 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
24 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
25 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
29 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
30 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
31 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
[all …]
/linux/drivers/tty/serial/8250/
H A D8250_tegra.c46 struct tegra_uart *uart; in tegra_uart_probe() local
51 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
52 if (!uart) in tegra_uart_probe()
84 uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in tegra_uart_probe()
85 if (IS_ERR(uart->rst)) in tegra_uart_probe()
86 return PTR_ERR(uart->rst); in tegra_uart_probe()
89 uart->clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
90 if (IS_ERR(uart->clk)) { in tegra_uart_probe()
95 ret = clk_prepare_enable(uart->clk); in tegra_uart_probe()
99 port->uartclk = clk_get_rate(uart->clk); in tegra_uart_probe()
[all …]
H A D8250_lpc18xx.c3 * Serial port driver for NXP LPC18xx/43xx UART
93 struct uart_8250_port uart; in lpc18xx_serial_probe() local
103 memset(&uart, 0, sizeof(uart)); in lpc18xx_serial_probe()
105 uart.port.membase = devm_ioremap(&pdev->dev, res->start, in lpc18xx_serial_probe()
107 if (!uart.port.membase) in lpc18xx_serial_probe()
116 dev_err(&pdev->dev, "uart clock not found\n"); in lpc18xx_serial_probe()
134 dev_err(&pdev->dev, "unable to enable uart clock\n"); in lpc18xx_serial_probe()
141 spin_lock_init(&uart.port.lock); in lpc18xx_serial_probe()
142 uart.port.dev = &pdev->dev; in lpc18xx_serial_probe()
143 uart.port.mapbase = res->start; in lpc18xx_serial_probe()
[all …]
H A D8250_ingenic.c6 * Ingenic SoC UART support
142 * oscillator and some peripherals including UART, which will in jz4750_early_console_setup()
153 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
156 OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart",
159 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
162 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
165 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
168 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
177 /* UART module enable */ in ingenic_uart_serial_out()
233 struct uart_8250_port uart = {}; in ingenic_uart_probe() local
[all …]
H A D8250_dfl.c3 * Driver for FPGA UART
52 static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart) in dfl_uart_get_params() argument
63 uart->port.uartclk = clk_freq; in dfl_uart_get_params()
71 uart->port.type = PORT_ALTR_16550_F32; in dfl_uart_get_params()
75 uart->port.type = PORT_ALTR_16550_F64; in dfl_uart_get_params()
79 uart->port.type = PORT_ALTR_16550_F128; in dfl_uart_get_params()
90 uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); in dfl_uart_get_params()
94 uart->port.iotype = UPIO_MEM32; in dfl_uart_get_params()
98 uart->port.iotype = UPIO_MEM16; in dfl_uart_get_params()
112 struct uart_8250_port uart = { }; in dfl_uart_probe() local
[all …]
H A D8250_hp300.c63 /* Offset to UART registers from base of DCA */
160 struct uart_8250_port uart; in hpdca_init_one() local
169 memset(&uart, 0, sizeof(uart)); in hpdca_init_one()
172 uart.port.iotype = UPIO_MEM; in hpdca_init_one()
173 uart.port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF; in hpdca_init_one()
174 uart.port.irq = d->ipl; in hpdca_init_one()
175 uart.port.uartclk = HPDCA_BAUD_BASE * 16; in hpdca_init_one()
176 uart.port.mapbase = (d->resource.start + UART_OFFSET); in hpdca_init_one()
177 uart.port.membase = (char *)(uart.port.mapbase + DIO_VIRADDRBASE); in hpdca_init_one()
178 uart.port.regshift = 1; in hpdca_init_one()
[all …]
H A D8250_pericom.c2 /* Driver for Pericom UART */
89 struct uart_8250_port uart; in pericom8250_probe() local
113 memset(&uart, 0, sizeof(uart)); in pericom8250_probe()
115 uart.port.dev = &pdev->dev; in pericom8250_probe()
116 uart.port.irq = pdev->irq; in pericom8250_probe()
117 uart.port.private_data = pericom; in pericom8250_probe()
118 uart.port.iotype = UPIO_PORT; in pericom8250_probe()
119 uart.port.uartclk = 921600 * 16; in pericom8250_probe()
120 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; in pericom8250_probe()
121 uart.port.set_divisor = pericom_do_set_divisor; in pericom8250_probe()
[all …]
/linux/arch/mips/kernel/
H A Dcps-vec-ns16550.S32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
67 * @t9: UART base address
69 * Write a single hexadecimal character to the UART.
82 * _mips_cps_putx8 - write an 8b hex value to the UART
[all …]
/linux/arch/arm/include/debug/
H A Dtegra.S45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
60 /* If clear, can't use UART; jump to save no UART */ \
62 /* Passed all tests, load address of UART registers */ \
63 ldr rp, =TEGRA_UART##uart##_BASE ; \
64 /* Jump to save UART address */ \
85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
89 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
[all …]
/linux/arch/arm/
H A DKconfig.debug120 UART definition, as specified below. Attempting to boot the kernel
137 bool "Kernel low-level debugging via asm9260 UART"
141 their output to an UART or USART port on asm9260 based
231 bool "Kernel low-level debugging on BCM2835 PL011 UART"
236 bool "Kernel low-level debugging on BCM2836 PL011 UART"
259 bool "Kernel low-level debugging messages via BCM KONA UART"
270 bool "Kernel low-level debugging on BCM63XX UART"
274 bool "Marvell Berlin SoC Debug UART"
282 bool "Use BRCMSTB UART for low-level debug"
287 UART physical and virtual address is automatically provided
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dmediatek,uart-dma.yaml4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
7 title: MediaTek UART APDMA controller
13 The MediaTek UART APDMA controller provides DMA capabilities
14 for the UART peripheral bus.
24 - mediatek,mt2712-uart-dma
25 - mediatek,mt6795-uart-dma
26 - mediatek,mt8365-uart-dma
27 - mediatek,mt8516-uart-dma
28 - const: mediatek,mt6577-uart-dma
30 - mediatek,mt6577-uart-dma
[all …]
/linux/drivers/tty/serial/
H A Dliteuart.c73 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_update_irq_reg() local
76 uart->irq_reg |= mask; in liteuart_update_irq_reg()
78 uart->irq_reg &= ~mask; in liteuart_update_irq_reg()
81 litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); in liteuart_update_irq_reg()
96 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_stop_rx() local
99 del_timer(&uart->timer); in liteuart_stop_rx()
133 struct liteuart_port *uart = data; in liteuart_interrupt() local
134 struct uart_port *port = &uart->port; in liteuart_interrupt()
143 isr = litex_read8(port->membase + OFF_EV_PENDING) & uart->irq_reg; in liteuart_interrupt()
155 struct liteuart_port *uart = from_timer(uart, t, timer); in liteuart_timer() local
[all …]
H A Dvt8500_serial.c28 * UART Register offsets
38 #define VT8500_URUSR 0x001c /* UART status */
96 struct uart_port uart; member
126 uart); in vt8500_stop_tx()
136 uart); in vt8500_stop_rx()
146 uart); in vt8500_enable_ms()
210 uart); in vt8500_start_tx()
282 container_of(port, struct vt8500_port, uart); in vt8500_set_baud_rate()
306 container_of(port, struct vt8500_port, uart); in vt8500_startup()
325 container_of(port, struct vt8500_port, uart); in vt8500_shutdown()
[all …]
/linux/tools/arch/x86/dell-uart-backlight-emulator/
H A DREADME1 Emulator for DELL0501 UART attached backlight controller
5 board connected to an UART.
7 In DSDT this uart port will be defined as:
12 With the DELL0501 indicating that we are dealing with an UART with
16 the drivers/platform/x86/dell/dell-uart-backlight.c driver without access
20 1. A (desktop) PC with a 16550 UART on the motherboard and a standard DB9
21 connector connected to this UART.
25 4. A DSDT overlay for the desktop PC replacing the _HID of the 16550 UART
32 ./dell-uart-backlight-emulator <path-to-/dev/tty*S#-for-second-port>
36 ./dell-uart-backlight-emulator /dev/ttyUSB0
[all …]
/linux/drivers/misc/ibmasm/
H A Duart.c22 struct uart_8250_port uart; in ibmasm_register_uart() local
27 /* read the uart scratch register to determine if the UART in ibmasm_register_uart()
31 dev_info(sp->dev, "IBM SP UART not registered, owned by service processor\n"); in ibmasm_register_uart()
36 memset(&uart, 0, sizeof(uart)); in ibmasm_register_uart()
37 uart.port.irq = sp->irq; in ibmasm_register_uart()
38 uart.port.uartclk = 3686400; in ibmasm_register_uart()
39 uart.port.flags = UPF_SHARE_IRQ; in ibmasm_register_uart()
40 uart.port.iotype = UPIO_MEM; in ibmasm_register_uart()
41 uart.port.membase = iomem_base; in ibmasm_register_uart()
43 sp->serial_line = serial8250_register_8250_port(&uart); in ibmasm_register_uart()

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