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/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A Dmmu.json3 "PublicDescription": "Level 2 data translation buffer allocation",
6 "BriefDescription": "Level 2 data translation buffer allocation"
9 "PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry",
12 "BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry"
15 "PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry",
18 "BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry"
21 "PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry",
24 "BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry"
27 "PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry",
30 "BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry"
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A Dmmu.json3 "PublicDescription": "Duration of a translation table walk handled by the MMU",
6 "BriefDescription": "Duration of a translation table walk handled by the MMU"
9 …"PublicDescription": "Duration of a Stage 1 translation table walk handled by the MMU. This event …
12 …"BriefDescription": "Duration of a Stage 1 translation table walk handled by the MMU. This event i…
15 …"PublicDescription": "Duration of a Stage 2 translation table walk handled by the MMU. This event …
18 …"BriefDescription": "Duration of a Stage 2 translation table walk handled by the MMU. This event i…
21 "PublicDescription": "Duration of a translation table walk requested by the LSU",
24 "BriefDescription": "Duration of a translation table walk requested by the LSU"
27 … "PublicDescription": "Duration of a translation table walk requested by the instruction side",
30 "BriefDescription": "Duration of a translation table walk requested by the instruction side"
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/
H A Dmmu.json3 "PublicDescription": "Duration of a translation table walk handled by the MMU",
6 "BriefDescription": "Duration of a translation table walk handled by the MMU"
9 "PublicDescription": "Duration of a Stage 1 translation table walk handled by the MMU",
12 "BriefDescription": "Duration of a Stage 1 translation table walk handled by the MMU"
15 "PublicDescription": "Duration of a Stage 2 translation table walk handled by the MMU",
18 "BriefDescription": "Duration of a Stage 2 translation table walk handled by the MMU"
21 "PublicDescription": "Duration of a translation table walk requested by the LSU",
24 "BriefDescription": "Duration of a translation table walk requested by the LSU"
27 … "PublicDescription": "Duration of a translation table walk requested by the Instruction Side",
30 "BriefDescription": "Duration of a translation table walk requested by the Instruction Side"
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A Dtlb.json4 … not count if the translation table walk results in a fault (such as a translation or access fault…
8 …translation table walk. This event will not count if the translation table walk results in a fault…
28 …"PublicDescription": "Counts data memory translation table walks caused by a miss in the L2 TLB dr…
32 …"PublicDescription": "Counts instruction memory translation table walks caused by a miss in the L2…
36 …translation table walk. This event will not count if the translation table walk results in a fault…
40 …translation table walk. This event will not count if the table walk results in a fault (such as a …
H A Dl2_cache.json4 …ruction accesses. Accesses are for misses in the first level caches or translation resolutions due…
8 …instruction accesses. Accesses are for misses in the level 1 caches or translation resolutions due…
20 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
24 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
28 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
32 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A Dtlb.json4 "PublicDescription": "Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB."
8 "PublicDescription": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an AT(address translation) instruction."
28 "PublicDescription": "Counts number of demand data translation table walks caused by a miss in the L2 TLB and performing at least one memory access. Translation tabl
[all...]
H A Dl2_cache.json4 "PublicDescription": "Counts accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level data cache or translation resolutions due to accesses. This event also counts write back of dirty data from level 1 data cache to the L2 cache."
8 "PublicDescription": "Counts cache line refills into the level 2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 data cache or translation resolutions due to accesses."
20 "PublicDescription": "Counts level 2 data cache accesses due to memory read operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses."
24 "PublicDescription": "Counts level 2 cache accesses due to memory write operations. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses."
28 "PublicDescription": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses."
32 "PublicDescription": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 data cache or translation resolutions due to accesses."
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dtlb.json4 … not count if the translation table walk results in a fault (such as a translation or access fault…
8 …translation table walk. This event will not count if the translation table walk results in a fault…
28 …"PublicDescription": "Counts data memory translation table walks caused by a miss in the L2 TLB dr…
32 …"PublicDescription": "Counts instruction memory translation table walks caused by a miss in the L2…
36 …translation table walk. This event will not count if the translation table walk results in a fault…
40 …translation table walk. This event will not count if the table walk results in a fault (such as a …
H A Dl2_cache.json4 …ruction accesses. Accesses are for misses in the first level caches or translation resolutions due…
8 …instruction accesses. Accesses are for misses in the level 1 caches or translation resolutions due…
20 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
24 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
28 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
32 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
/linux/arch/arm/mm/
H A Dfsr-3level.c7 { do_bad, SIGBUS, 0, "reserved translation fault" },
8 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
9 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
10 { do_page_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
23 { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
24 { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
25 { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
26 { do_bad, SIGBUS, 0, "synchronous abort (translation table walk)" },
31 { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
32 { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk" },
[all …]
H A Dfsr-2level.c12 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "section translation fault" },
14 { do_page_fault, SIGSEGV, SEGV_MAPERR, "page translation fault" },
19 { do_bad, SIGBUS, 0, "external abort on translation" },
21 { do_bad, SIGBUS, 0, "external abort on translation" },
52 { do_translation_fault, SIGSEGV, SEGV_MAPERR, "section translation fault" },
54 { do_page_fault, SIGSEGV, SEGV_MAPERR, "page translation fault" },
59 { do_bad, SIGBUS, 0, "external abort on translation" },
61 { do_bad, SIGBUS, 0, "external abort on translation" },
/linux/Documentation/translations/
H A Dindex.rst27 Translation's purpose is to ease reading and understanding in languages other
37 no guarantee that a translation is up to date. If what you read in a
38 translation does not sound right compared to what you read in the code, please
39 inform the translation maintainer and - if you can - check also the English
42 A translation is not a fork of the official documentation, therefore
47 accept only contributions that are merely translation related (e.g. new
52 grammar and culture, so the translation of an English statement may need to be
58 comfortable writing in English, you can ask the translation's maintainers
/linux/drivers/mtd/
H A DKconfig30 comment "User Modules And Translation Layers"
76 tristate "FTL (Flash Translation Layer) support"
80 This provides support for the original Flash Translation Layer which
93 tristate "NFTL (NAND Flash Translation Layer) support"
97 This provides support for the NAND Flash Translation Layer which is
113 Support for writing to the NAND Flash Translation Layer, as used
117 tristate "INFTL (Inverse NAND Flash Translation Layer) support"
121 This provides support for the Inverse NAND Flash Translation
135 tristate "Resident Flash Disk (Flash Translation Layer) support"
139 This provides support for the flash translation layer known
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dpipeline.json35 …oup (Distant) due to a marked data side request. When using Radix Page Translation, this count exc…
40 … L2 without conflict due to a data side request. When using Radix Page Translation, this count exc…
80 …the same chip due to a marked data side request. When using Radix Page Translation, this count exc…
95 … L2 on the same chip due to a data side request. When using Radix Page Translation, this count exc…
115 …n Mepf state. due to a marked data side request. When using Radix Page Translation, this count exc…
160 …e or distant) due to a marked data side request. When using Radix Page Translation, this count exc…
175 …th dispatch conflict due to a data side request. When using Radix Page Translation, this count exc…
180 …hout conflict due to a marked data side request. When using Radix Page Translation, this count exc…
185 … cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation"
225 …hout conflict due to a marked data side request. When using Radix Page Translation, this count exc…
[all …]
H A Dpmc.json20 … as this chip due to a marked data side request. When using Radix Page Translation, this count exc…
30 … the local core's L3 due to a data side request. When using Radix Page Translation, this count exc…
40 …al core's L2 due to a marked data side request.. When using Radix Page Translation, this count exc…
90 …al remote or distant due to a data side request. When using Radix Page Translation, this count exc…
95 …atch conflict due to a marked data side request. When using Radix Page Translation, this count exc…
100 …cal core's L3 due to a marked data side request. When using Radix Page Translation, this count exc…
110 …ocal chip's L4 cache due to a data side request. When using Radix Page Translation, this count exc…
H A Dmarked.json20 … L3 on the same chip due to a data side request. When using Radix Page Translation, this count exc…
45 …ore's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation"
50 …ore's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation"
60 …p's L4 cache due to a marked data side request.. When using Radix Page Translation, this count exc…
70 …the same chip due to a marked data side request. When using Radix Page Translation, this count exc…
95 …the same chip due to a marked data side request. When using Radix Page Translation, this count exc…
100 … L3 on the same chip due to a data side request. When using Radix Page Translation, this count exc…
210 …chip's Memory due to a marked data side request. When using Radix Page Translation, this count exc…
220 …cal core's L3 due to a marked data side request. When using Radix Page Translation, this count exc…
225 …k cache from the core's L3 data cache. This is the deepest level of PWC possible for a translation"
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Dvirtual-memory.json23 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
32 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
41 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
50 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
84 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
93 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
102 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
111 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
170 …ription": "Counts the number of times there was an ITLB miss and a new translation was filled into…
174 …he machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB)…
[all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A Dvirtual-memory.json23 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
32 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
41 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
50 …ads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffe…
84 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
93 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
102 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
111 …walks completed due to stores whose address translations missed in all Translation Lookaside Buffe…
170 …ription": "Counts the number of times there was an ITLB miss and a new translation was filled into…
174 …he machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB)…
[all …]
/linux/Documentation/doc-guide/
H A Dchecktransupdate.rst3 Checking for needed translation updates
6 This script helps track the translation status of the documentation in
14 translation commit (order by author date) and the latest English commits
23 - track the translation status of files that have no translation
46 No translation in the locale of zh_CN
/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A Dextended.json84 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
112 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
119 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
126 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
133 …on": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry ar…
140 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segmen…
/linux/tools/perf/pmu-events/arch/s390/cf_z10/
H A Dextended.json77 …"PublicDescription": "A translation entry has been written into the Level-1 Instruction Translatio…
84 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
91 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
98 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segmen…
105 …on": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry ar…
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A Dcache.json156 …che. If a single translation table walk needs to make multiple accesses to the IPA cache, each acc…
159 …che. If a single translation table walk needs to make multiple accesses to the IPA cache, each acc…
162 …ingle translation table walk needs to make multiple accesses to the IPA cache, each access that ca…
165 …ingle translation table walk needs to make multiple accesses to the IPA cache, each access that ca…
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A Dextended.json42 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
70 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
77 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
84 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
91 …on": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry ar…
98 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segmen…
/linux/Documentation/scsi/
H A Daha152x.rst33 EXT_TRANS: enable extended translation (0/1: default 0 [off])
116 enable extended translation for first and second controller
152 This is considered to be the default translation.
157 extended translation. This means that the BIOS uses 255 for heads,
163 To make it even more complicated the translation mode might/might
169 - for disks<1GB: use default translation (C/32/64)
175 ie. either (C/32/64) or (C/63/255)). This can be extended translation
178 - if that fails, take extended translation if enabled by override,
179 kernel or module parameter, otherwise take default translation and
/linux/arch/s390/include/uapi/asm/
H A Dsie.h50 { 0x0010, "Prog Segment translation" }, \
51 { 0x0011, "Prog Page translation" }, \
52 { 0x0012, "Prog Translation specification" }, \
60 { 0x0020, "Prog AFX translation" }, \
61 { 0x0021, "Prog ASX translation" }, \
62 { 0x0022, "Prog LX translation" }, \
63 { 0x0023, "Prog EX translation" }, \
69 { 0x0029, "Prog ALEN translation" }, \
81 { 0x0039, "Prog Region first translation" }, \
82 { 0x003A, "Prog Region second translation" }, \
[all …]

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