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/linux/drivers/devfreq/
H A Dtegra30-devfreq.c3 * A devfreq driver for NVIDIA Tegra SoCs
22 #include <soc/tegra/fuse.h>
218 static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset) in actmon_readl() argument
220 return readl_relaxed(tegra->regs + offset); in actmon_readl()
223 static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset) in actmon_writel() argument
225 writel_relaxed(val, tegra->regs + offset); in actmon_writel()
251 static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra, in tegra_devfreq_update_avg_wmark() argument
254 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()
255 u32 band = avg_band_freq * tegra->devfreq->profile->polling_ms; in tegra_devfreq_update_avg_wmark()
265 static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra, in tegra_devfreq_update_wmark() argument
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/linux/drivers/clk/tegra/
H A Dclk-tegra124-emc.c3 * drivers/clk/tegra/clk-emc.c
14 #include <linux/clk/tegra.h>
25 #include <soc/tegra/fuse.h>
94 struct tegra_clk_emc *tegra; in emc_recalc_rate() local
97 tegra = container_of(hw, struct tegra_clk_emc, hw); in emc_recalc_rate()
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
118 struct tegra_clk_emc *tegra; in emc_determine_rate() local
123 tegra = container_of(hw, struct tegra_clk_emc, hw); in emc_determine_rate()
125 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
126 if (tegra->timings[k].ram_code == ram_code) in emc_determine_rate()
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/linux/drivers/soc/tegra/
H A Dregulators-tegra20.c10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
21 #include <soc/tegra/fuse.h>
22 #include <soc/tegra/pmc.h>
44 static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, in tegra20_core_limit() argument
62 if (tegra_pmc_core_domain_state_synced() && !tegra->sys_reboot_mode) { in tegra20_core_limit()
67 if (tegra->core_min_uV > 0) in tegra20_core_limit()
68 return tegra->core_min_uV; in tegra20_core_limit()
85 tegra->core_min_uV = core_max_uV; in tegra20_core_limit()
87 pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); in tegra20_core_limit()
89 return tegra->core_min_uV; in tegra20_core_limit()
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H A Dregulators-tegra30.c10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
21 #include <soc/tegra/fuse.h>
22 #include <soc/tegra/pmc.h>
43 static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, in tegra30_core_limit() argument
61 if (tegra_pmc_core_domain_state_synced() && !tegra->sys_reboot_mode) { in tegra30_core_limit()
66 if (tegra->core_min_uV > 0) in tegra30_core_limit()
67 return tegra->core_min_uV; in tegra30_core_limit()
84 tegra->core_min_uV = core_max_uV; in tegra30_core_limit()
86 pr_info("core voltage initialized to %duV\n", tegra->core_min_uV); in tegra30_core_limit()
88 return tegra->core_min_uV; in tegra30_core_limit()
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/linux/drivers/clocksource/
H A Dtimer-tegra186.c113 static struct tegra186_tmr *tegra186_tmr_create(struct tegra186_timer *tegra, in tegra186_tmr_create() argument
119 tmr = devm_kzalloc(tegra->dev, sizeof(*tmr), GFP_KERNEL); in tegra186_tmr_create()
123 tmr->parent = tegra; in tegra186_tmr_create()
124 tmr->regs = tegra->regs + offset; in tegra186_tmr_create()
148 struct tegra186_timer *tegra = wdt->tmr->parent; in tegra186_wdt_enable() local
153 writel(value, tegra->regs + TKEIE(wdt->tmr->hwirq)); in tegra186_wdt_enable()
300 static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *tegra, in tegra186_wdt_create() argument
308 offset += tegra->soc->num_timers * 0x10000 + index * 0x10000; in tegra186_wdt_create()
310 wdt = devm_kzalloc(tegra->dev, sizeof(*wdt), GFP_KERNEL); in tegra186_wdt_create()
314 wdt->regs = tegra->regs + offset; in tegra186_wdt_create()
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/linux/drivers/gpu/drm/tegra/
H A Ddrm.c36 #define DRIVER_NAME "tegra"
37 #define DRIVER_DESC "NVIDIA Tegra graphics"
77 struct tegra_drm *tegra = drm->dev_private; in tegra_atomic_commit_tail() local
79 if (tegra->hub) { in tegra_atomic_commit_tail()
461 struct tegra_drm *tegra = drm->dev_private; in tegra_open_channel() local
473 list_for_each_entry(client, &tegra->clients, list) in tegra_open_channel()
856 struct tegra_drm *tegra = drm->dev_private; in tegra_debugfs_iova() local
859 if (tegra->domain) { in tegra_debugfs_iova()
860 mutex_lock(&tegra->mm_lock); in tegra_debugfs_iova()
861 drm_mm_print(&tegra->mm, &p); in tegra_debugfs_iova()
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/linux/drivers/memory/tegra/
H A DMakefile2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
10 tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
11 tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o
12 tegra-mc-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186.o tegra234.o
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/linux/sound/soc/tegra/
H A DKconfig2 menu "Tegra" menu
5 tristate "SoC Audio for the Tegra System-on-Chip"
12 Say Y or M here if you want support for SoC audio on Tegra.
184 tristate "Audio Graph Card based Tegra driver"
187 Config to enable Tegra audio machine driver based on generic
189 few things for Tegra audio. Most of the code is re-used from
196 tristate "SoC Audio support for Tegra boards using an RT5631 codec"
201 Say Y or M here if you want to add support for SoC audio on Tegra
205 tristate "SoC Audio support for Tegra boards using an RT5640 codec"
210 Say Y or M here if you want to add support for SoC audio on Tegra
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/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra-audio-max98090.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-max98090.yaml#
7 title: NVIDIA Tegra audio complex with MAX98090 CODEC
14 - $ref: nvidia,tegra-audio-common.yaml#
20 - pattern: '^[a-z0-9]+,tegra-audio-max98090(-[a-z0-9]+)+$'
21 - const: nvidia,tegra-audio-max98090
24 - nvidia,tegra-audio-max98090-nyan-big
25 - nvidia,tegra-audio-max98090-nyan-blaze
26 - const: nvidia,tegra-audio-max98090-nyan
27 - const: nvidia,tegra-audio-max98090
78 compatible = "nvidia,tegra-audio-max98090-venice2",
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H A Dnvidia,tegra-audio-max9808x.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-max9808x.yaml#
7 title: NVIDIA Tegra audio complex with MAX9808x CODEC
14 - $ref: nvidia,tegra-audio-common.yaml#
20 - pattern: '^[a-z0-9]+,tegra-audio-max98088(-[a-z0-9]+)+$'
21 - const: nvidia,tegra-audio-max98088
23 - pattern: '^[a-z0-9]+,tegra-audio-max98089(-[a-z0-9]+)+$'
24 - const: nvidia,tegra-audio-max98089
65 #include <dt-bindings/soc/tegra-pmc.h>
67 compatible = "lg,tegra-audio-max98089-p895",
68 "nvidia,tegra-audio-max98089";
H A Dnvidia,tegra-audio-wm8903.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm8903.yaml#
7 title: NVIDIA Tegra audio complex with WM8903 CODEC
14 - $ref: nvidia,tegra-audio-common.yaml#
20 - pattern: '^[a-z0-9]+,tegra-audio-wm8903(-[a-z0-9]+)+$'
21 - const: nvidia,tegra-audio-wm8903
23 - pattern: ad,tegra-audio-plutux
24 - const: nvidia,tegra-audio-wm8903
69 compatible = "nvidia,tegra-audio-wm8903-harmony",
70 "nvidia,tegra-audio-wm8903";
71 nvidia,model = "tegra-wm8903-harmony";
H A Dnvidia,tegra-audio-wm8753.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm8753.yaml#
7 title: NVIDIA Tegra audio complex with WM8753 CODEC
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-wm8753(-[a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-wm8753
66 compatible = "nvidia,tegra-audio-wm8753-whistler",
67 "nvidia,tegra-audio-wm8753";
68 nvidia,model = "tegra-wm8753-harmony";
H A Dnvidia,tegra-audio-rt5640.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-rt5640.yaml#
7 title: NVIDIA Tegra audio complex with RT5639 or RT5640 CODEC
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-rt56(39|40)(-[a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-rt5640
65 compatible = "nvidia,tegra-audio-rt5640-dalmore",
66 "nvidia,tegra-audio-rt5640";
67 nvidia,model = "NVIDIA Tegra Dalmore";
H A Dnvidia,tegra-audio-rt5631.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-rt5631.yaml#
7 title: NVIDIA Tegra audio complex with RT5631 CODEC
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-rt5631(-[a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-rt5631
63 #include <dt-bindings/soc/tegra-pmc.h>
65 compatible = "asus,tegra-audio-rt5631-tf700t",
66 "nvidia,tegra-audio-rt5631";
H A Dnvidia,tegra-audio-rt5677.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-rt5677.yaml#
7 title: NVIDIA Tegra audio complex with RT5677 CODEC
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-rt5677(-[a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-rt5677
74 compatible = "nvidia,tegra-audio-rt5677-ryu",
75 "nvidia,tegra-audio-rt5677";
76 nvidia,model = "NVIDIA Tegra Ryu";
H A Dnvidia,tegra-audio-alc5632.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-alc5632.yaml#
7 title: NVIDIA Tegra audio complex with ALC5632 CODEC
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-alc5632(-[a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-alc5632
56 compatible = "nvidia,tegra-audio-alc5632-paz00",
57 "nvidia,tegra-audio-alc5632";
H A Dnvidia,tegra-audio-wm9712.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm9712.yaml#
7 title: NVIDIA Tegra audio complex with WM9712 CODEC
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-wm9712([-_][a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-wm9712
61 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
62 "nvidia,tegra-audio-wm9712";
H A Dnvidia,tegra-audio-sgtl5000.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-sgtl5000.yaml#
7 title: NVIDIA Tegra audio complex with SGTL5000 CODEC
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-sgtl5000([-_][a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-sgtl5000
54 compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
55 "nvidia,tegra-audio-sgtl5000";
/linux/drivers/crypto/tegra/
H A DMakefile4 tegra-se-objs := tegra-se-key.o tegra-se-main.o
6 tegra-se-y += tegra-se-aes.o
7 tegra-se-y += tegra-se-hash.o
9 obj-$(CONFIG_CRYPTO_DEV_TEGRA) += tegra-se.o
/linux/drivers/firmware/tegra/
H A DMakefile2 tegra-bpmp-y = bpmp.o
3 tegra-bpmp-$(CONFIG_ARCH_TEGRA_210_SOC) += bpmp-tegra210.o
4 tegra-bpmp-$(CONFIG_ARCH_TEGRA_186_SOC) += bpmp-tegra186.o
5 tegra-bpmp-$(CONFIG_ARCH_TEGRA_194_SOC) += bpmp-tegra186.o
6 tegra-bpmp-$(CONFIG_ARCH_TEGRA_234_SOC) += bpmp-tegra186.o
7 tegra-bpmp-$(CONFIG_ARCH_TEGRA_264_SOC) += bpmp-tegra186.o
8 tegra-bpmp-$(CONFIG_DEBUG_FS) += bpmp-debugfs.o
9 obj-$(CONFIG_TEGRA_BPMP) += tegra-bpmp.o
/linux/drivers/phy/tegra/
H A DMakefile2 obj-$(CONFIG_PHY_TEGRA_XUSB) += phy-tegra-xusb.o
4 phy-tegra-xusb-y += xusb.o
5 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o
6 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o
7 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o
8 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o
9 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o
10 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_234_SOC) += xusb-tegra186.o
/linux/Documentation/gpu/
H A Dtegra.rst2 drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
10 Up until, but not including, Tegra124 (aka Tegra K1) the drm/tegra driver
15 The drm/tegra driver supports NVIDIA Tegra SoC generations since Tegra20. It
65 Tegra SoC generations, up until Tegra186 which introduces several changes that
71 Tegra SoCs have two display controllers, each of which can be associated with
100 The type and number of supported outputs varies between Tegra SoC generations.
116 HDMI is supported on all Tegra SoCs. Starting with Tegra210, HDMI is provided
123 Although Tegra has supported DSI since Tegra30, the controller has changed in
126 later are supported by the drm/tegra driver.
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/linux/Documentation/devicetree/bindings/regulator/
H A Dnvidia,tegra-regulators-coupling.txt1 NVIDIA Tegra Regulators Coupling
4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
28 - nvidia,tegra-cpu-regulator: Boolean property that designates regulator
42 nvidia,tegra-core-regulator;
52 nvidia,tegra-rtc-regulator;
62 nvidia,tegra-cpu-regulator;
/linux/drivers/soc/tegra/fuse/
H A Dspeedo-tegra30.c10 #include <soc/tegra/fuse.h>
91 pr_debug("Tegra ATE prog ver %d.%d\n", ate_ver/10, ate_ver%10); in fuse_speedo_calib()
143 pr_err("Tegra Unknown pkg %d\n", package_id); in rev_sku_to_speedo_ids()
160 pr_err("Tegra Unknown pkg %d\n", package_id); in rev_sku_to_speedo_ids()
177 pr_err("Tegra Unknown pkg %d\n", package_id); in rev_sku_to_speedo_ids()
214 pr_err("Tegra Unknown pkg %d\n", package_id); in rev_sku_to_speedo_ids()
219 pr_warn("Tegra Unknown SKU %d\n", sku_info->sku_id); in rev_sku_to_speedo_ids()
227 pr_warn("Tegra Unknown chip rev %d\n", sku_info->revision); in rev_sku_to_speedo_ids()
249 pr_debug("Tegra CPU speedo value %u\n", cpu_speedo_val); in tegra30_init_speedo_data()
250 pr_debug("Tegra Core speedo value %u\n", soc_speedo_val); in tegra30_init_speedo_data()
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/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
7 title: Tegra Power Management Controller (PMC)
27 # Tegra clock of the same name
38 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink
39 control which allows 32Khz clock output to Tegra blink pad.
43 include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs.
126 description: The vast majority of hardware blocks of Tegra SoC belong to a
153 of the Tegra K1 Technical Reference Manual.
184 the powergates on the Tegra SoC. Each powergate node represents a power-
185 domain on the Tegra SoC that can be power-gated by the Tegra PMC.
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