| /linux/drivers/phy/starfive/ |
| H A D | phy-jh7110-dphy-rx.c | 66 struct clk *tx_clk; member
124 clk_set_rate(dphy->tx_clk, 19800000); in stf_dphy_power_on()
175 dphy->tx_clk = devm_clk_get(&pdev->dev, "tx"); in stf_dphy_probe()
176 if (IS_ERR(dphy->tx_clk)) in stf_dphy_probe()
177 return PTR_ERR(dphy->tx_clk); in stf_dphy_probe()
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | cdns,macb.yaml | 87 - const: tx_clk
188 clock-names = "pclk", "hclk", "tx_clk";
216 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
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| H A D | intel,dwmac-plat.yaml | 42 - const: tx_clk
110 clock-names = "stmmaceth", "ptp_ref", "tx_clk";
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| H A D | qcom-emac.txt | 44 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
93 "mdio_clk", "tx_clk", "rx_clk", "sys_clk";
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| /linux/drivers/net/ethernet/cadence/ |
| H A D | macb_main.c | 526 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG)) in macb_set_tx_clk()
547 rate_rounded = clk_round_rate(bp->tx_clk, rate); in macb_set_tx_clk()
561 if (clk_set_rate(bp->tx_clk, rate_rounded)) in macb_set_tx_clk()
562 netdev_err(bp->dev, "adjusting tx_clk failed.\n"); in macb_set_tx_clk()
3999 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk, in macb_clks_disable() argument
4007 { .clk = tx_clk }, in macb_clks_disable()
4014 struct clk **hclk, struct clk **tx_clk, in macb_clk_init() argument
4039 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk"); in macb_clk_init()
4040 if (IS_ERR(*tx_clk)) in macb_clk_init()
4041 return PTR_ERR(*tx_clk); in macb_clk_init()
[all …]
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| H A D | macb.h | 1197 struct clk **hclk, struct clk **tx_clk,
1278 struct clk *tx_clk; member
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| /linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | microchip,ksz.yaml | 71 MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
77 Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI,
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| /linux/drivers/net/dsa/sja1105/ |
| H A D | sja1105_clocking.c | 303 /* Per MII spec, the PHY (which is us) drives the TX_CLK pin */ in sja1105_mii_clocking_setup()
416 pad_mii_tx.clk_os = 3; /* TX_CLK output stage */ in sja1105_rgmii_cfg_pad_tx_config()
417 pad_mii_tx.clk_ih = 0; /* TX_CLK input hysteresis (default) */ in sja1105_rgmii_cfg_pad_tx_config()
418 pad_mii_tx.clk_ipud = 2; /* TX_CLK input stage (default) */ in sja1105_rgmii_cfg_pad_tx_config()
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| /linux/arch/powerpc/boot/dts/ |
| H A D | mpc832x_rdb.dts | 180 3 23 2 0 1 0 /* TX_CLK (CLK3) */
200 3 24 2 0 1 0 /* TX_CLK (CLK10) */
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| /linux/arch/arm/boot/dts/intel/socfpga/ |
| H A D | socfpga_arria10_socdk.dtsi | 75 * for TX_CLK on Arria 10.
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| /linux/arch/arm/boot/dts/xilinx/ |
| H A D | zynq-7000.dtsi | 253 clock-names = "pclk", "hclk", "tx_clk";
264 clock-names = "pclk", "hclk", "tx_clk";
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| /linux/drivers/net/ethernet/intel/e1000/ |
| H A D | e1000_ethtool.c | 1120 /* Because we reset the PHY above, we need to re-force TX_CLK in the in e1000_phy_reset_clk_and_crs()
1166 /* Have to setup TX_CLK and TX_CRS after software reset */ in e1000_nonintegrated_phy_loopback()
1174 /* Have to setup TX_CLK and TX_CRS after software reset */ in e1000_nonintegrated_phy_loopback()
1185 /* Setup TX_CLK and TX_CRS one more time. */ in e1000_nonintegrated_phy_loopback()
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| H A D | e1000_hw.h | 2768 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2769 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2770 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
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| H A D | e1000_hw.c | 1257 /* Force TX_CLK in the Extended PHY Specific Control Register in e1000_copper_link_mgp_setup()
1825 /* Because we reset the PHY above, we need to re-force TX_CLK in in e1000_phy_force_speed_duplex()
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| /linux/drivers/net/phy/ |
| H A D | micrel.c | 1017 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
1021 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
1103 u16 rx, tx, rx_clk, tx_clk; in ksz9031_config_rgmii_delay() local
1109 tx_clk = TX_CLK_ND; in ksz9031_config_rgmii_delay()
1115 tx_clk = TX_CLK_ID; in ksz9031_config_rgmii_delay()
1121 tx_clk = TX_CLK_ND; in ksz9031_config_rgmii_delay()
1127 tx_clk = TX_CLK_ID; in ksz9031_config_rgmii_delay()
1158 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) | in ksz9031_config_rgmii_delay()
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| /linux/drivers/net/ethernet/intel/igb/ |
| H A D | e1000_phy.c | 580 /* Force TX_CLK in the Extended PHY Specific Control Register in igb_copper_link_setup_m88()
1194 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1297 /* Resetting the phy means we need to re-force TX_CLK in the in igb_phy_force_speed_duplex_m88()
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| H A D | e1000_defines.h | 946 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
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| /linux/drivers/net/ethernet/intel/e1000e/ |
| H A D | phy.c | 796 /* Force TX_CLK in the Extended PHY Specific Control Register in e1000e_copper_link_setup_m88()
1291 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1371 /* Resetting the phy means we need to re-force TX_CLK in the in e1000e_phy_force_speed_duplex_m88()
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| H A D | defines.h | 747 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
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| H A D | 80003es2lan.c | 583 /* Resetting the phy means we need to verify the TX_CLK corresponds in e1000_phy_force_speed_duplex_80003es2lan()
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| /linux/arch/arm/boot/dts/microchip/ |
| H A D | sama7g5.dtsi | 855 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
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| /linux/drivers/pinctrl/renesas/ |
| H A D | pfc-r8a7740.c | 1918 * TXD[0:3], TX_CLK, TX_EN, TX_ER
1934 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
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| /linux/drivers/net/dsa/b53/ |
| H A D | b53_common.c | 1284 * tx_clk aligned timing (restoring to reset defaults) in b53_adjust_531x5_rgmii()
|