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Searched full:tve (Results 1 – 22 of 22) sorted by relevance

/linux/Documentation/devicetree/bindings/display/
H A Dfaraday,tve200.yaml29 - const: TVE
61 clock-names = "PCLK", "TVE";
H A Dsimple-framebuffer.yaml143 - mixer1-lcd1-tve
/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_tcon_top.c187 * channel clock. Parent could be either TCON TV or TVE clock. For now in sun8i_tcon_top_bind()
188 * we leave this fixed to TCON TV, since TVE driver for R40 is not yet in sun8i_tcon_top_bind()
190 * if TVE is active on each TCON TV. If it is, mux should be switched in sun8i_tcon_top_bind()
191 * to TVE clock parent. in sun8i_tcon_top_bind()
H A Dsun4i_tv.c564 .name = "sun4i-tve",
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-mba53.dts228 &tve {
232 fsl,tve-mode = "vga";
H A Dimx53.dtsi813 tve: tve@63ff0000 { label
814 compatible = "fsl,imx53-tve";
819 clock-names = "tve", "di_sel";
H A Dimx53-qsb.dts109 &tve {
/linux/drivers/gpu/drm/imx/ipuv3/
H A DMakefile8 obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
/linux/drivers/clk/sunxi-ng/
H A Dccu-suniv-f1c100s.c174 static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb",
294 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2",
297 static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2",
H A Dccu-sun20i-d1.c768 static SUNXI_CCU_MP_HW_WITH_MUX_GATE(tve_clk, "tve", tcon_tve_parents, 0xbb0,
775 static SUNXI_CCU_GATE_HWS(bus_tve_top_clk, "bus-tve-top", psi_ahb_hws,
777 static SUNXI_CCU_GATE_HWS(bus_tve_clk, "bus-tve", psi_ahb_hws,
H A Dccu-sun5i.c280 static SUNXI_CCU_GATE(ahb_tve_clk, "ahb-tve", "ahb",
442 static SUNXI_CCU_GATE(dram_tve_clk, "dram-tve", "pll-ddr",
H A Dccu-sun8i-h3.c270 static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb1",
466 static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
H A Dccu-sun50i-h616.c696 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb3",
/linux/drivers/gpu/drm/tve200/
H A Dtve200_drv.c189 priv->clk = devm_clk_get(dev, "TVE"); in tve200_probe()
191 dev_err(dev, "unable to get TVE clock\n"); in tve200_probe()
H A Dtve200_drm.h96 #define TVE200_TVEEN BIT(0) /* Enable TVE block */
/linux/drivers/gpu/ipu-v3/
H A Dipu-di.c337 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ in ipu_di_sync_config_noninterlaced()
354 .offset_count = 1, /* magic value from Freescale TVE driver */ in ipu_di_sync_config_noninterlaced()
363 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ in ipu_di_sync_config_noninterlaced()
372 .offset_count = 1, /* magic value from Freescale TVE driver */ in ipu_di_sync_config_noninterlaced()
/linux/arch/powerpc/platforms/powernv/
H A Dpci-ioda.c1048 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1052 * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1055 * devices in TVE#0.
1057 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1108 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); in pnv_pci_ioda_dma_64bit_bypass()
1135 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to in pnv_pci_ioda_iommu_bypass_supported()
1292 * Map TCE table through TVT. The TVE index is the PE number in pnv_pci_ioda2_set_window()
1593 /* TVE #1 is selected by PCI address bit 59 */ in pnv_pci_ioda2_setup_dma_pe()
/linux/drivers/clk/ingenic/
H A Djz4755-cgu.c175 "tve", CGU_CLK_MUX | CGU_CLK_GATE,
H A Djz4760-cgu.c235 "tve", CGU_CLK_GATE | CGU_CLK_MUX,
H A Djz4780-cgu.c692 "tve", CGU_CLK_GATE,
/linux/arch/arm/boot/dts/allwinner/
H A Dsunxi-h3-h5.dtsi71 framebuffer-tve {
74 allwinner,pipeline = "mixer1-lcd1-tve";
/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi435 clock-names = "PCLK", "TVE";