1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Markus Niebel 6 */ 7 8#include "imx93.dtsi" 9 10/{ 11 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM"; 12 compatible = "tq,imx93-tqma9352", "fsl,imx93"; 13 14 memory@80000000 { 15 device_type = "memory"; 16 /* our minimum RAM config will be 1024 MiB */ 17 reg = <0x00000000 0x80000000 0 0x40000000>; 18 }; 19 20 reserved-memory { 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges; 24 25 linux,cma { 26 compatible = "shared-dma-pool"; 27 reusable; 28 alloc-ranges = <0 0x80000000 0 0x40000000>; 29 size = <0 0x10000000>; 30 linux,cma-default; 31 }; 32 }; 33 34 /* SD2 RST# via PMIC SW_EN */ 35 reg_usdhc2_vmmc: regulator-usdhc2 { 36 compatible = "regulator-fixed"; 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 39 regulator-name = "VSD_3V3"; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 vin-supply = <&buck4>; 43 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 44 enable-active-high; 45 }; 46}; 47 48&adc1 { 49 vref-supply = <&buck5>; 50}; 51 52&flexspi1 { 53 pinctrl-names = "default"; 54 pinctrl-0 = <&pinctrl_flexspi1>; 55 status = "okay"; 56 57 flash0: flash@0 { 58 compatible = "jedec,spi-nor"; 59 reg = <0>; 60 /* 61 * no DQS, RXCLKSRC internal loop back, max 66 MHz 62 * clk framework uses CLK_DIVIDER_ROUND_CLOSEST 63 * selected value together with root from 64 * IMX93_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to 65 * respect the maximum value. 66 */ 67 spi-max-frequency = <62000000>; 68 spi-tx-bus-width = <4>; 69 spi-rx-bus-width = <4>; 70 vcc-supply = <&buck5>; 71 72 partitions { 73 compatible = "fixed-partitions"; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 }; 77 }; 78}; 79 80&lpi2c1 { 81 clock-frequency = <400000>; 82 pinctrl-names = "default", "sleep"; 83 pinctrl-0 = <&pinctrl_lpi2c1>; 84 pinctrl-1 = <&pinctrl_lpi2c1>; 85 status = "okay"; 86 87 se97_som: temperature-sensor@1b { 88 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 89 reg = <0x1b>; 90 }; 91 92 pca9451a: pmic@25 { 93 compatible = "nxp,pca9451a"; 94 reg = <0x25>; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_pca9451>; 97 interrupt-parent = <&gpio1>; 98 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 99 100 regulators { 101 /* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */ 102 buck1: BUCK1 { 103 regulator-name = "BUCK1"; 104 regulator-min-microvolt = <750000>; 105 regulator-max-microvolt = <900000>; 106 regulator-boot-on; 107 regulator-always-on; 108 regulator-ramp-delay = <3125>; 109 }; 110 111 /* V_DDRQ - 0.6 V for LPDDR4X */ 112 buck2: BUCK2 { 113 regulator-name = "BUCK2"; 114 regulator-min-microvolt = <600000>; 115 regulator-max-microvolt = <600000>; 116 regulator-boot-on; 117 regulator-always-on; 118 regulator-ramp-delay = <3125>; 119 }; 120 121 /* V_3V3 - EEPROM, RTC, ... */ 122 buck4: BUCK4 { 123 regulator-name = "BUCK4"; 124 regulator-min-microvolt = <3300000>; 125 regulator-max-microvolt = <3300000>; 126 regulator-boot-on; 127 regulator-always-on; 128 }; 129 130 /* V_1V8 - SPI NOR, eMMC, RAM VDD1... */ 131 buck5: BUCK5 { 132 regulator-name = "BUCK5"; 133 regulator-min-microvolt = <1800000>; 134 regulator-max-microvolt = <1800000>; 135 regulator-boot-on; 136 regulator-always-on; 137 }; 138 139 /* V_1V1 - RAM VDD2*/ 140 buck6: BUCK6 { 141 regulator-name = "BUCK6"; 142 regulator-min-microvolt = <1100000>; 143 regulator-max-microvolt = <1100000>; 144 regulator-boot-on; 145 regulator-always-on; 146 }; 147 148 /* V_1V8_BBSM, fix 1.8 */ 149 ldo1: LDO1 { 150 regulator-name = "LDO1"; 151 regulator-min-microvolt = <1800000>; 152 regulator-max-microvolt = <1800000>; 153 regulator-boot-on; 154 regulator-always-on; 155 }; 156 157 /* V_0V8_ANA */ 158 ldo4: LDO4 { 159 regulator-name = "LDO4"; 160 regulator-min-microvolt = <800000>; 161 regulator-max-microvolt = <800000>; 162 regulator-boot-on; 163 regulator-always-on; 164 }; 165 166 /* V_SD2 - 3.3/1.8V USDHC2 io Voltage */ 167 ldo5: LDO5 { 168 regulator-name = "LDO5"; 169 regulator-min-microvolt = <1800000>; 170 regulator-max-microvolt = <3300000>; 171 regulator-boot-on; 172 regulator-always-on; 173 }; 174 }; 175 }; 176 177 pcf85063: rtc@51 { 178 compatible = "nxp,pcf85063a"; 179 reg = <0x51>; 180 quartz-load-femtofarads = <7000>; 181 }; 182 183 eeprom0: eeprom@53 { 184 compatible = "nxp,se97b", "atmel,24c02"; 185 reg = <0x53>; 186 pagesize = <16>; 187 read-only; 188 vcc-supply = <&buck4>; 189 }; 190 191 eeprom1: eeprom@57 { 192 compatible = "atmel,24c64"; 193 reg = <0x57>; 194 pagesize = <32>; 195 vcc-supply = <&buck4>; 196 }; 197 198 /* protectable identification memory (part of M24C64-D @57) */ 199 eeprom@5f { 200 compatible = "atmel,24c64d-wl"; 201 reg = <0x5f>; 202 vcc-supply = <&buck4>; 203 }; 204 205 imu@6a { 206 compatible = "st,ism330dhcx"; 207 reg = <0x6a>; 208 vdd-supply = <&buck4>; 209 vddio-supply = <&buck4>; 210 }; 211}; 212 213&usdhc1 { 214 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 215 pinctrl-0 = <&pinctrl_usdhc1>; 216 pinctrl-1 = <&pinctrl_usdhc1>; 217 pinctrl-2 = <&pinctrl_usdhc1>; 218 vmmc-supply = <&buck4>; 219 vqmmc-supply = <&buck5>; 220 bus-width = <8>; 221 non-removable; 222 no-sdio; 223 no-sd; 224 status = "okay"; 225}; 226 227&wdog3 { 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_wdog>; 230 fsl,ext-reset-output; 231 status = "okay"; 232}; 233 234&iomuxc { 235 pinctrl_flexspi1: flexspi1grp { 236 fsl,pins = < 237 /* FSEL 3 | DSE X6 */ 238 MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x01fe 239 MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x01fe 240 /* HYS | PU | FSEL 3 | DSE X6 */ 241 MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x13fe 242 MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x13fe 243 /* HYS | FSEL 3 | DSE X6 (external PU) */ 244 MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x11fe 245 MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x11fe 246 >; 247 }; 248 249 pinctrl_lpi2c1: lpi2c1grp { 250 fsl,pins = < 251 /* SION | OD | FSEL 3 | DSE X4 */ 252 MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x4000199e 253 MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x4000199e 254 >; 255 }; 256 257 pinctrl_pca9451: pca9451grp { 258 fsl,pins = < 259 /* HYS | PU */ 260 MX93_PAD_I2C2_SDA__GPIO1_IO03 0x1200 261 >; 262 }; 263 264 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 265 fsl,pins = < 266 /* FSEL 2 | DSE X2 */ 267 MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x106 268 >; 269 }; 270 271 /* enable SION for data and cmd pad due to ERR052021 */ 272 pinctrl_usdhc1: usdhc1grp { 273 fsl,pins = < 274 /* PD | FSEL 3 | DSE X4 */ 275 MX93_PAD_SD1_CLK__USDHC1_CLK 0x59e 276 /* HYS | FSEL 0 | no drive */ 277 MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1000 278 /* HYS | PU | FSEL 3 | DSE X4 */ 279 MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e 280 /* HYS | PU | FSEL 3 | DSE X4 */ 281 MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e 282 MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e 283 MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000139e 284 MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e 285 MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e 286 MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e 287 MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e 288 MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e 289 >; 290 }; 291 292 pinctrl_wdog: wdoggrp { 293 fsl,pins = < 294 /* PU | FSEL 1 | DSE X4 */ 295 MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e 296 >; 297 }; 298}; 299