| /linux/Documentation/devicetree/bindings/thermal/ |
| H A D | samsung,exynos-thermal.yaml | 7 title: Samsung Exynos SoC Thermal Management Unit (TMU)
13 For multi-instance tmu each instance should have an alias correctly numbered
19 - samsung,exynos3250-tmu
20 - samsung,exynos4412-tmu
21 - samsung,exynos4210-tmu
22 - samsung,exynos5250-tmu
23 - samsung,exynos5260-tmu
24 # For TMU channel 0, 1 on Exynos5420:
25 - samsung,exynos5420-tmu
26 # For TMU channels 2, 3 and 4 of Exynos5420:
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| H A D | qoriq-thermal.yaml | 7 title: Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
19 The version of the device is determined by the TMU IP Block Revision
26 - fsl,qoriq-tmu
27 - fsl,imx8mq-tmu
35 fsl,tmu-range:
43 fsl,tmu-calibration:
59 boolean, if present, the TMU registers are little endian. If absent,
73 - fsl,tmu-range
74 - fsl,tmu-calibration
80 tmu@f0000 {
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| /linux/drivers/clocksource/ |
| H A D | sh_tmu.c | 3 * SuperH Timer Support - TMU
39 struct sh_tmu_device *tmu; member
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
111 switch (ch->tmu->model) { in sh_tmu_write()
113 return iowrite8(value, ch->tmu->mapbase + 2); in sh_tmu_write()
115 return iowrite8(value, ch->tmu->mapbase + 4); in sh_tmu_write()
132 raw_spin_lock_irqsave(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
141 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
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| /linux/drivers/thunderbolt/ |
| H A D | tmu.c | 3 * Thunderbolt Time Management Unit (TMU) support
73 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_set_tmu_mode_params()
81 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_set_tmu_mode_params()
86 sw->tmu.cap + TMU_RTR_CS_15, 1); in tb_switch_set_tmu_mode_params()
100 sw->tmu.cap + TMU_RTR_CS_15, 1); in tb_switch_set_tmu_mode_params()
108 sw->tmu.cap + TMU_RTR_CS_18, 1); in tb_switch_set_tmu_mode_params()
116 sw->tmu.cap + TMU_RTR_CS_18, 1); in tb_switch_set_tmu_mode_params()
128 sw->tmu.cap + TMU_RTR_CS_0, 1); in tb_switch_tmu_ucap_is_supported()
141 sw->tmu.cap + TMU_RTR_CS_3, 1); in tb_switch_tmu_rate_read()
155 sw->tmu.cap + TMU_RTR_CS_3, 1); in tb_switch_tmu_rate_write()
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| H A D | tb.h | 79 * enum tb_switch_tmu_mode - TMU mode
80 * @TB_SWITCH_TMU_MODE_OFF: TMU is off
86 * Ordering is based on TMU accuracy level (highest last).
97 * struct tb_switch_tmu - Structure holding router TMU configuration
98 * @cap: Offset to the TMU capability (%0 if not found)
100 * @mode: TMU mode related to the upstream router. Reflects the HW
102 * @mode_request: TMU mode requested to set. Related to upstream router.
121 * @tmu: The switch TMU configuration
135 * @cap_vsec_tmu: Offset to the TMU vendor specific capability (%0 if not found)
176 struct tb_switch_tmu tmu; member
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| /linux/drivers/gpu/drm/v3d/ |
| H A D | v3d_perfmon.c | 30 …{"QPU", "QPU-total-clk-cycles-waiting-TMU", "[QPU] Total clock cycles for all QPUs stalled waiting…
37 {"TMU", "TMU-total-text-quads-access", "[TMU] Total texture cache accesses"},
38 …{"TMU", "TMU-total-text-cache-miss", "[TMU] Total texture cache misses (number of fetches from mem…
62 {"TMU", "TMU-total-config-access", "[TMU] Total config accesses"},
65 {"L2T", "L2T-TMU-writes", "[L2T] TMU write accesses"},
66 {"TMU", "TMU-active-cycles", "[TMU] Active cycles"},
67 {"TMU", "TMU-stalled-cycles", "[TMU] Stalled cycles"},
69 {"L2T", "L2T-TMU-reads", "[L2T] TMU read accesses"},
72 {"L2T", "L2T-TMU-config-reads", "[L2T] TMU CFG read accesses"},
76 {"L2T", "L2T-TMU-write-miss", "[L2T] TMU write misses"},
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| /linux/Documentation/driver-api/thermal/ |
| H A D | exynos_thermal.rst | 14 TMU controller Description:
46 TMU(Thermal Management Unit) in Exynos4/5 generates interrupt
64 TMU driver description:
74 TMU configuration data -----> TMU Driver <----> Exynos Core thermal wrapper
78 a) TMU configuration data:
79 This consist of TMU register offsets/bitfields
82 are used to configure the TMU.
83 b) TMU driver:
84 This component initialises the TMU controller and sets different
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| /linux/drivers/platform/x86/intel/ |
| H A D | bxtwc_tmu.c | 3 * Intel BXT Whiskey Cove PMIC TMU driver
7 * This driver adds TMU (Time Management Unit) support for Intel BXT platform.
8 * It enables the alarm wake-up functionality in the TMU unit of Whiskey Cove
38 /* Read TMU interrupt reg */ in bxt_wcove_tmu_irq_handler()
41 /* clear TMU irq */ in bxt_wcove_tmu_irq_handler()
74 /* Unmask TMU second level Wake & System alarm */ in bxt_wcove_tmu_probe()
87 /* Mask TMU interrupts */ in bxt_wcove_tmu_remove()
136 MODULE_DESCRIPTION("BXT Whiskey Cove TMU Driver");
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| /linux/drivers/gpu/drm/vc4/ |
| H A D | vc4_validate_shaders.c | 31 * (reading it as a texture, uniform data, or direct-addressed TMU
159 int tmu) in record_texture_sample() argument
172 &validation_state->tmu_setup[tmu], in record_texture_sample()
179 validation_state->tmu_setup[tmu].p_offset[i] = ~0; in record_texture_sample()
195 int tmu = waddr > QPU_W_TMU0_B; in check_tmu_write() local
197 bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0; in check_tmu_write()
205 DRM_DEBUG("direct TMU read used small immediate\n"); in check_tmu_write()
214 DRM_DEBUG("direct TMU load wasn't an add\n"); in check_tmu_write()
225 DRM_DEBUG("direct TMU load wasn't clamped\n"); in check_tmu_write()
231 DRM_DEBUG("direct TMU load wasn't clamped\n"); in check_tmu_write()
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| /linux/arch/sh/kernel/cpu/ |
| H A D | clock-cpg.c | 60 clk_add_alias("fck", "sh-tmu-sh3.0", "peripheral_clk", NULL); in cpg_clk_init()
61 clk_add_alias("fck", "sh-tmu.0", "peripheral_clk", NULL); in cpg_clk_init()
62 clk_add_alias("fck", "sh-tmu.1", "peripheral_clk", NULL); in cpg_clk_init()
63 clk_add_alias("fck", "sh-tmu.2", "peripheral_clk", NULL); in cpg_clk_init()
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| /linux/drivers/thermal/samsung/ |
| H A D | Kconfig | 7 If you say yes here you get support for the TMU (Thermal Management
9 the TMU, reports temperature and handles cooling action if defined.
10 This driver uses the Exynos core thermal APIs and TMU configuration
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| /linux/arch/sh/kernel/cpu/sh4a/ |
| H A D | clock-sh7786.c | 155 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
156 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]),
157 CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP010]),
158 CLKDEV_ICK_ID("fck", "sh-tmu.3", &mstp_clks[MSTP011]),
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| H A D | setup-sh7770.c | 228 .name = "sh-tmu",
249 .name = "sh-tmu",
270 .name = "sh-tmu",
354 TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC, enumerator
407 INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
425 DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
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| H A D | clock-sh7734.c | 91 MSTP016, MSTP015, MSTP014, /* TMU / TIMER */
201 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]),
202 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP015]),
203 CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP014]),
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| H A D | clock-sh7757.c | 123 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP113]),
124 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP114]),
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| H A D | clock-shx3.c | 124 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
125 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]),
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| H A D | setup-sh7734.c | 193 /* TMU */
206 .name = "sh-tmu",
227 .name = "sh-tmu",
248 .name = "sh-tmu",
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| H A D | clock-sh7785.c | 146 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
147 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]),
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-ls1043a.dtsi | 160 thermal-sensors = <&tmu 0>;
180 thermal-sensors = <&tmu 1>;
200 thermal-sensors = <&tmu 2>;
220 thermal-sensors = <&tmu 3>;
251 thermal-sensors = <&tmu 4>;
444 tmu: tmu@1f00000 { label
445 compatible = "fsl,qoriq-tmu";
448 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
449 fsl,tmu-calibration =
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| /linux/arch/powerpc/boot/dts/fsl/ |
| H A D | t1023si-post.dtsi | 365 tmu: tmu@f0000 { label
366 compatible = "fsl,qoriq-tmu";
369 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
370 fsl,tmu-calibration =
418 thermal-sensors = <&tmu 0>;
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| H A D | t1040si-post.dtsi | 445 tmu: tmu@f0000 { label
446 compatible = "fsl,qoriq-tmu";
449 fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
450 fsl,tmu-calibration =
494 thermal-sensors = <&tmu 2>;
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5420.dtsi | 944 tmu_cpu0: tmu@10060000 {
945 compatible = "samsung,exynos5420-tmu";
953 tmu_cpu1: tmu@10064000 {
954 compatible = "samsung,exynos5420-tmu";
962 tmu_cpu2: tmu@10068000 {
963 compatible = "samsung,exynos5420-tmu-ext-triminfo";
971 tmu_cpu3: tmu@1006c000 {
972 compatible = "samsung,exynos5420-tmu-ext-triminfo";
980 tmu_gpu: tmu@100a0000 {
981 compatible = "samsung,exynos5420-tmu-ext-triminfo";
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| /linux/arch/arm/boot/dts/renesas/ |
| H A D | r8a7792.dtsi | 360 compatible = "renesas,tmu-r8a7792", "renesas,tmu";
374 compatible = "renesas,tmu-r8a7792", "renesas,tmu";
389 compatible = "renesas,tmu-r8a7792", "renesas,tmu";
404 compatible = "renesas,tmu-r8a7792", "renesas,tmu";
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r8a77995.dtsi | 350 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
364 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
379 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
394 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
408 compatible = "renesas,tmu-r8a77995", "renesas,tmu";
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| /linux/include/dt-bindings/thermal/ |
| H A D | thermal_exynos.h | 3 * thermal_exynos.h - Samsung Exynos TMU device tree definitions
|