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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_tmds_clk.c69 struct sun4i_tmds *tmds = hw_to_tmds(hw); in sun4i_tmds_determine_rate() local
88 for (j = tmds->div_offset ?: 1; in sun4i_tmds_determine_rate()
89 j < (16 + tmds->div_offset); j++) { in sun4i_tmds_determine_rate()
128 struct sun4i_tmds *tmds = hw_to_tmds(hw); in sun4i_tmds_recalc_rate() local
131 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); in sun4i_tmds_recalc_rate()
135 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); in sun4i_tmds_recalc_rate()
136 reg = ((reg >> 4) & 0xf) + tmds->div_offset; in sun4i_tmds_recalc_rate()
146 struct sun4i_tmds *tmds = hw_to_tmds(hw); in sun4i_tmds_set_rate() local
151 sun4i_tmds_calc_divider(rate, parent_rate, tmds->div_offset, in sun4i_tmds_set_rate()
154 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); in sun4i_tmds_set_rate()
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H A Dsun8i_dw_hdmi.c136 hdmi->clk_tmds = devm_clk_get(dev, "tmds"); in sun8i_dw_hdmi_bind()
139 "Couldn't get the tmds clock\n"); in sun8i_dw_hdmi_bind()
160 dev_err(dev, "Could not enable tmds clock\n"); in sun8i_dw_hdmi_bind()
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi-qp.c45 * The values for TMDS 25175, 25200, 27000, 54000, 74250 and 148500 kHz are
50 unsigned long tmds; member
55 { .tmds = 25175000, .n_32k = 4576, .n_44k1 = 7007, .n_48k = 6864, },
56 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
57 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
58 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
59 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
60 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
61 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
62 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_combios.c94 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
95 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
339 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ in combios_get_table_offset()
348 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ in combios_get_table_offset()
1300 struct radeon_encoder_int_tmds *tmds) in radeon_legacy_get_tmds_info_from_table() argument
1307 tmds->tmds_pll[i].value = in radeon_legacy_get_tmds_info_from_table()
1309 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; in radeon_legacy_get_tmds_info_from_table()
1316 struct radeon_encoder_int_tmds *tmds) in radeon_legacy_get_tmds_info_from_combios() argument
1334 tmds->tmds_pll[i].value = in radeon_legacy_get_tmds_info_from_combios()
1336 tmds->tmds_pll[i].freq = in radeon_legacy_get_tmds_info_from_combios()
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H A Dradeon_mode.h257 /* legacy TMDS PLL detect */
409 /* legacy int tmds */
414 /* tmds over dvo */
857 struct radeon_encoder_int_tmds *tmds);
859 struct radeon_encoder_int_tmds *tmds);
861 struct radeon_encoder_int_tmds *tmds);
863 struct radeon_encoder_ext_tmds *tmds);
865 struct radeon_encoder_ext_tmds *tmds);
/linux/include/media/i2c/
H A Dtc358743.h80 /* Reset PHY automatically when TMDS clock goes from DC to AC.
86 /* Reset PHY automatically when TMDS clock passes 21 MHz.
92 /* Reset PHY automatically when TMDS clock is detected.
H A Dadv7842.h181 /* 0 = Mode 0: run when there is no TMDS clock
182 1 = Mode 1: run when there is no TMDS clock or the
/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun8i-a83t-dw-hdmi.yaml52 - description: TMDS Clock
62 - const: tmds
170 clock-names = "iahb", "isfr", "tmds";
227 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
/linux/drivers/video/fbdev/via/
H A Dchip.h64 /* Definition TMDS Trasmitter Information */
67 /* Definition TMDS Trasmitter Index */
72 /* Definition TMDS Trasmitter I2C Target Address */
H A Ddvi.c81 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n"); in viafb_tmds_trasmitter_identify()
91 DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n"); in viafb_tmds_trasmitter_identify()
107 DEBUG_MSG(KERN_INFO "\n Integrated TMDS ! \n"); in viafb_tmds_trasmitter_identify()
317 /* Turn off TMDS power. */ in viafb_dvi_disable()
455 /* Turn on TMDS power. */ in viafb_dvi_enable()
/linux/drivers/gpu/drm/tests/
H A Ddrm_kunit_edid.h28 * DFP 1.x compatible TMDS
106 * DFP 1.x compatible TMDS
148 * Maximum TMDS clock: 100 MHz
159 …* CTA-861: The maximum HDMI TMDS clock is 100000 kHz, but one or more video timings go up to 148…
219 * DFP 1.x compatible TMDS
261 * Maximum TMDS clock: 200 MHz
327 * DFP 1.x compatible TMDS
369 * Maximum TMDS clock: 340 MHz
435 * DFP 1.x compatible TMDS
483 * Maximum TMDS clock: 200 MHz
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H A Ddrm_connector_test.c1509 * Test that for a given mode, with 8bpc and an RGB output the TMDS
1530 * Test that for a given mode, with 10bpc and an RGB output the TMDS
1551 * Test that for the VIC-1 mode, with 10bpc and an RGB output the TMDS
1569 * Test that for a given mode, with 12bpc and an RGB output the TMDS
1590 * Test that for the VIC-1 mode, with 12bpc and an RGB output the TMDS
1608 * Test that for a mode with the pixel repetition flag, the TMDS
1629 * Test that the TMDS character rate computation for the VIC modes
1666 * with 10bpc, the TMDS character rate is equal to 0.625 times the mode
1691 * with 12bpc, the TMDS character rate is equal to 0.75 times the mode
1715 * Test that for a given mode, the computation of the TMDS character
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/linux/drivers/gpu/drm/sti/
H A Dsti_hdmi_tx3g4c28phy.c96 DRM_ERROR("input TMDS clock speed (%d) not supported\n", in sti_hdmi_tx3g4c28phy_start()
106 DRM_ERROR("output TMDS clock (%d) out of range\n", tmdsck); in sti_hdmi_tx3g4c28phy_start()
143 * for different high speed TMDS clock frequencies a phy configuration in sti_hdmi_tx3g4c28phy_start()
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bios.c144 * conf byte. These tables are similar to the TMDS tables, consisting in run_lvds_table()
630 * This runs the TMDS regs setting code found on BIT bios cards in run_tmds_table()
643 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ in run_tmds_table()
650 clktable = bios->tmds.output0_script_ptr; in run_tmds_table()
654 clktable = bios->tmds.output1_script_ptr; in run_tmds_table()
666 NV_ERROR(drm, "TMDS output init script not found\n"); in run_tmds_table()
905 * Parses the pointer to the TMDS table in parse_bit_tmds_tbl_entry()
909 * offset + 0 (16 bits): TMDS table pointer in parse_bit_tmds_tbl_entry()
911 * The TMDS table is typically found just before the DCB table, with a in parse_bit_tmds_tbl_entry()
931 NV_ERROR(drm, "Do not understand BIT TMDS table\n"); in parse_bit_tmds_tbl_entry()
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H A Dnouveau_bios.h118 uint16_t fptablepointer; /* also used by tmds */
142 } tmds; member
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgm200.c78 ior->tmds.high_speed = khz > 340000; in gm200_sor_hdmi_scdc()
81 if (ior->tmds.high_speed) in gm200_sor_hdmi_scdc()
83 if (ior->tmds.high_speed || scrambling_low_rates) in gm200_sor_hdmi_scdc()
H A Dg94.c158 if (sor->asy.proto == TMDS) { in g94_sor_war_needed()
277 case 1: state->proto = TMDS; state->link = 1; break; in g94_sor_state()
278 case 2: state->proto = TMDS; state->link = 2; break; in g94_sor_state()
279 case 5: state->proto = TMDS; state->link = 3; break; in g94_sor_state()
H A Dior.h29 TMDS, enumerator
46 /* Armed TMDS state. */
49 } tmds; member
H A Dga102.c91 if (sor->asy.proto == TMDS) { in ga102_sor_clock()
92 if (sor->tmds.high_speed) in ga102_sor_clock()
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h104 * Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
141 * used when TMDS CLK rate = TMDS character rate /4. Default 0.
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix-anx78xx.h104 * TMDS Control
107 /* TMDS Control Registers */
109 /* Bits for TMDS Control Register 7 */
/linux/drivers/gpu/drm/amd/display/include/
H A Dsignal_types.h29 /* Minimum pixel clock, in KHz. For TMDS signal is 25.00 MHz */
31 /* Maximum pixel clock, in KHz. For TMDS signal is 165.00 MHz */
/linux/drivers/gpu/drm/nouveau/include/nvif/
H A Dif0012.h29 } tmds; member
136 } tmds; member
/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos-hdmi.yaml118 - description: Gate of HDMI TMDS clock.
120 - description: TMDS clock generated by HDMI-PHY.
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dinit.c539 init_tmds_reg(struct nvbios_init *init, u8 tmds) in init_tmds_reg() argument
541 /* For mlv < 0x80, it is an index into a table of TMDS base addresses. in init_tmds_reg()
554 if (tmds >= 0x80) { in init_tmds_reg()
557 if (tmds == 0x81) in init_tmds_reg()
563 error("tmds opcodes need dcb\n"); in init_tmds_reg()
565 if (tmds < ARRAY_SIZE(pramdac_table)) in init_tmds_reg()
566 return pramdac_table[tmds]; in init_tmds_reg()
568 error("tmds selector 0x%02x unknown\n", tmds); in init_tmds_reg()
1096 u8 tmds = nvbios_rd08(bios, init->offset + 1); in init_tmds() local
1100 u32 reg = init_tmds_reg(init, tmds); in init_tmds()
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