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/freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/
H A D	translation.json	5 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G", 11 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M", 17 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K", 23 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K", 29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data… 47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the lo… 53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d… 59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… [all …]
H A D	marked.json	329 "BriefDescription": "Erat Miss (TLB Access) All page sizes", 335 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G", 341 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M", 347 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 4K", 353 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K", 365 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 371 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 377 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ… 383 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the … 389 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a mark… [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a75/
H A D	cache.json	129 "PublicDescription": "Level 1 PLD TLB refill", 132 "BriefDescription": "Level 1 PLD TLB refill" 135 …"PublicDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwa… 138 …"BriefDescription": "Level 2 preload and MMU prefetcher TLB access. This event only counts softwar… 141 "PublicDescription": "Level 1 TLB flush", 144 "BriefDescription": "Level 1 TLB flush" 147 "PublicDescription": "Level 2 TLB access", 150 "BriefDescription": "Level 2 TLB access" 153 …eload TLB access. This event only counts software and hardware prefetches at Level 1. This event c… 156 …eload TLB access. This event only counts software and hardware prefetches at Level 1. This event c… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A D	virtual-memory.json	9 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 26 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 32 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 43 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 54 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 65 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 87 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 104 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 110 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 121 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/
H A D	virtual-memory.json	8 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 18 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 39 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 49 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 59 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 69 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 89 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 99 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 115 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylake/
H A D	virtual-memory.json	8 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 18 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 39 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 49 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 59 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 69 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 89 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 99 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 115 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A D	virtual-memory.json	8 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 18 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 34 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 39 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 49 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 59 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 69 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 89 … a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the wal… 99 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 115 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A D	virtual-memory.json	9 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 28 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 34 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 46 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 58 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 70 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 94 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 113 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 119 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 131 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/icelake/
H A D	virtual-memory.json	9 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 28 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 34 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 46 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 58 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 82 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 101 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 107 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 119 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 131 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tigerlake/
H A D	virtual-memory.json	9 …blicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).… 26 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 32 …emand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can … 43 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 54 …This implies address translations missed in the DTLB and further levels of TLB. The page walk can … 76 …ublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 93 …"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page s… 99 …mand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can … 110 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to … 121 …mpleted due to demand data stores whose address translations missed in the TLB and were mapped to … [all …]
/freebsd/sys/contrib/device-tree/Bindings/nios2/
H A D	nios2.txt	`23 - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB. 24 - altr,tlb-num-entries: Specifies the number of entries in the TLB. 25 - altr,tlb-ptr-sz: Specifies size of TLB pointer. 30 - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address 52 altr,tlb-num-ways = <16>; 53 altr,tlb [all...]`
/freebsd/sys/netinet/
H A D	tcp_log_buf.c	268 #define TCPID_BUCKET_LOCK_INIT(tlb) mtx_init(&((tlb)->tlb_mtx), "tcp log id bucket", NULL, MTX_DEF) argument 269 #define TCPID_BUCKET_LOCK_DESTROY(tlb) mtx_destroy(&((tlb)->tlb_mtx)) argument 270 #define TCPID_BUCKET_LOCK(tlb) mtx_lock(&((tlb)->tlb_mtx)) argument 271 #define TCPID_BUCKET_UNLOCK(tlb) mtx_unlock(&((tlb)->tlb_mtx)) argument 272 #define TCPID_BUCKET_LOCK_ASSERT(tlb) mtx_assert(&((tlb)->tlb_mtx), MA_OWNED) argument 273 #define TCPID_BUCKET_UNLOCK_ASSERT(tlb) mtx_assert(&((tlb)->tlb_mtx), MA_NOTOWNED) argument 275 #define TCPID_BUCKET_REF(tlb) refcount_acquire(&((tlb)->tlb_refcnt)) argument 276 #define TCPID_BUCKET_UNREF(tlb) refcount_release(&((tlb)->tlb_refcnt)) argument 379 tcp_log_remove_bucket(struct tcp_log_id_bucket *tlb) in tcp_log_remove_bucket() argument 383 KASSERT(SLIST_EMPTY(&tlb->tlb_head), in tcp_log_remove_bucket() [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a73/
H A D	cache.json	`72 "PublicDescription": "Level 1 PLD TLB refill", 75 "BriefDescription": "Level 1 PLD TLB refill" 78 "PublicDescription": "Level 1 CP15 TLB refill", 81 "BriefDescription": "Level 1 CP15 TLB refill" 84 "PublicDescription": "Level 1 TLB flush", 87 "BriefDescription": "Level 1 TLB flush" 90 "PublicDescription": "Level 2 TLB access", 93 "BriefDescription": "Level 2 TLB access" 96 "PublicDescription": "Level 2 TLB miss", 99 "BriefDescription": "Level 2 TLB miss"`
/freebsd/sys/contrib/device-tree/src/riscv/sifive/
H A D	fu540-c000.dtsi	`48 d-tlb-sets = <1>; 49 d-tlb-size = <32>; 54 i-tlb-sets = <1>; 55 i-tlb-size = <32>; 62 tlb-split; 75 d-tlb-sets = <1>; 76 d-tlb-size = <32>; 81 i-tlb-sets = <1>; 82 i-tlb-size = <32>; 89 tlb [all...]`
H A D	fu740-c000.dtsi	`49 d-tlb-sets = <1>; 50 d-tlb-size = <40>; 55 i-tlb-sets = <1>; 56 i-tlb-size = <40>; 64 tlb-split; 76 d-tlb-sets = <1>; 77 d-tlb-size = <40>; 82 i-tlb-sets = <1>; 83 i-tlb-size = <40>; 91 tlb [all...]`
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A D	virtual-memory.json	14 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to load… 31 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 43 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 55 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 67 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 96 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor… 113 …res whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 125 …res whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 137 …res whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 149 …res whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A D	pipeline.json	15 …n issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there… 18 …n issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there… 63 …he backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a… 66 …he backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a… 75 …e backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a… 78 …e backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a…
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A D	pipeline.json	35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ… 40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 80 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 95 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 110 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K" 115 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa… 120 …"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radi… 160 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro… 175 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch… 180 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/ampere/emag/
H A D	cache.json	69 …PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB", 71 "BriefDescription": "L1D TLB access" 74 …ublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB", 78 …"PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts … 81 "BriefDescription": "L2D TLB access" 84 …"PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event … 87 "BriefDescription": "L2I TLB access" 126 "PublicDescription": "Level 1 stage 2 TLB refill", 129 "BriefDescription": "L1 stage 2 TLB refill"
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/
H A D	ifu.json	9 …"PublicDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l… 12 …"BriefDescription": "Counts the cycles spent on a request for Level 2 TLB lookup after a Level 1l … 57 "PublicDescription": "Thread flushed due to TLB miss", 60 "BriefDescription": "Thread flushed due to TLB miss" 63 "PublicDescription": "Thread flushed due to reasons other than TLB miss", 66 "BriefDescription": "Thread flushed due to reasons other than TLB miss" 81 … other thread was also active, but not necessarily ready. For example, waiting for I-Cache or TLB", 84 …e other thread was also active, but not necessarily ready. For example, waiting for I-Cache or TLB" 87 … arbitrated because it was not ready for scheduling. For example, due to a cache miss or TLB miss", 90 …t arbitrated because it was not ready for scheduling. For example, due to a cache miss or TLB miss"
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a76-n1/
H A D	cache.json	7 …cDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This inclu… 19 …"PublicDescription": "This event counts any refill of the data L1 TLB from the L2 TLB. This includ… 47 … "This event counts any load or store operation which accesses the data L1 TLB. If both a load and… 49 "BriefDescription": "Level 1 data TLB access." 52 …"This event counts any instruction fetch which accesses the instruction L1 TLB.This event counts r… 54 "BriefDescription": "Level 1 instruction TLB access" 72 …"PublicDescription": "This event counts on anyrefill of the L2 TLB, caused by either an instructio… 74 "BriefDescription": "Attributable L2 data or unified TLB refill" 77 …"PublicDescription": "This event counts on any access to the L2 TLB (caused by a refill of any of …
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/
H A D	pipeline.json	27 …e to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty… 30 …e to the frontend, TLB miss. This event counts every cycle that the DPU instruction queue is empty… 75 …e backend, load, TLB miss. This event counts every cycle where there is a stall in the Wr stage du… 78 …e backend, load, TLB miss. This event counts every cycle where there is a stall in the Wr stage du… 87 … store, TLB miss. This event counts every cycle where there is a stall in the Wr stage because of … 90 … store, TLB miss. This event counts every cycle where there is a stall in the Wr stage because of …
/freebsd/lib/libpmc/pmu-events/arch/x86/silvermont/
H A D	virtual-memory.json	`17 …I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB m… 36 …age walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses … 55 …age walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses … 65 …age walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses …`
/freebsd/sys/contrib/device-tree/src/riscv/microchip/
H A D	microchip-mpfs.dtsi	`41 d-tlb-sets = <1>; 42 d-tlb-size = <32>; 47 i-tlb-sets = <1>; 48 i-tlb-size = <32>; 53 tlb-split; 68 d-tlb-sets = <1>; 69 d-tlb-size = <32>; 74 i-tlb-sets = <1>; 75 i-tlb-size = <32>; 80 tlb-split; [all …]`
/freebsd/lib/libpmc/pmu-events/arch/x86/elkhartlake/
H A D	virtual-memory.json	14 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to load… 31 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 43 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 55 …es) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 91 …res whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 103 …res whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were ma… 127 … Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", 139 … Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", 151 … Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", 163 … Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", [all …]

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