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/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Drpmh-rsc.txt2 ------------
6 can be written to the Trigger Command Set (TCS) registers and using a (addr,
7 val) pair and triggered. Messages in the TCS are then sent in sequence over an
16 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
17 have powered off to facilitate idle power saving. TCS could be classified as -
35 - compatible:
38 Definition: Should be "qcom,rpmh-rsc".
40 - reg:
42 Value type: <prop-encoded-array>
45 The tcs-offset specifies the start address of the
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H A Dqcom,rpmh-rsc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 resources can be written to the Trigger Command Set (TCS) registers and
16 using a (addr, val) pair and triggered. Messages in the TCS are then sent in
25 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
26 have powered off to facilitate idle power saving. TCS could be classified as::
27 ACTIVE - Triggered by Linux
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/freebsd/contrib/atf/atf-c++/
H A Datf-c++.329 .Nm atf-c++ ,
63 .Nd C++ API to write ATF-based test programs
66 .Fn ATF_ADD_TEST_CASE "tcs" "name"
69 .Fn ATF_INIT_TEST_CASES "tcs"
145 C++-based test programs follow this template:
146 .Bd -literal -offset indent
148 \&... C-specific includes go here ...
151 \&... C++-specific includes go here ...
153 #include <atf-c++.hpp>
187 ATF_INIT_TEST_CASES(tcs)
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/freebsd/sys/amd64/sgx/
H A Dsgx.c1 /*-
7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
61 * Adds TCS, REG pages to the enclave.
66 * .-- ECREATE -- Add SECS page
67 * Kernel | EADD -- Add TCS, REG pages
68 * space | EEXTEND -- Measure the page (take unique hash)
69 * ENCLS | EPA -- Allocate version array page
70 * '-- EINIT -- Finalize enclave creation
71 * User .-- EENTER -- Go to entry point of enclave
72 * space | EEXIT -- Exit back to main application
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/freebsd/contrib/atf/atf-c/
H A Datf-c.329 .Nm atf-c ,
95 .Nd C API to write ATF-based test programs
289 C-based test programs follow this template:
290 .Bd -literal -offset indent
291 \&... C-specific includes go here ...
293 #include <atf-c.h>
329 ATF_TP_ADD_TC(tcs, tc1);
330 ATF_TP_ADD_TC(tcs, tc2);
331 ATF_TP_ADD_TC(tcs, tc3);
341 .Xr atf-test-case 4 .
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/freebsd/sys/dev/ice/
H A Dice_dcb.c1 /* SPDX-License-Identifier: BSD-3-Clause */
41 * @buf: pointer to the caller-supplied buffer to store the MIB block
65 cmd->type = mib_type & ICE_AQ_LLDP_MIB_TYPE_M; in ice_aq_get_lldp_mib()
66 cmd->type |= (bridge_type << ICE_AQ_LLDP_BRID_TYPE_S) & in ice_aq_get_lldp_mib()
74 *local_len = LE16_TO_CPU(cmd->local_len); in ice_aq_get_lldp_mib()
76 *remote_len = LE16_TO_CPU(cmd->remote_len); in ice_aq_get_lldp_mib()
103 cmd->comman in ice_aq_cfg_lldp_mib_change()
184 ice_aq_update_lldp_tlv(struct ice_hw * hw,u8 bridge_type,void * buf,u16 buf_size,u16 old_len,u16 new_len,u16 offset,u16 * mib_len,struct ice_sq_cd * cd) ice_aq_update_lldp_tlv() argument
295 u8 offset = 0; ice_parse_ieee_ets_common_tlv() local
421 u16 offset = 0; ice_parse_ieee_app_tlv() local
514 u16 offset = 0; ice_parse_cee_pgcfg_tlv() local
595 u16 len, typelen, offset = 0; ice_parse_cee_app_tlv() local
737 u16 offset = 0; ice_lldp_to_dcb_cfg() local
1311 u8 offset = 0; ice_add_ieee_ets_common_tlv() local
1469 u16 typelen, len, offset = 0; ice_add_ieee_app_pri_tlv() local
1581 u8 offset = 0; ice_add_dscp_tc_bw_tlv() local
1702 u16 len, offset = 0, tlvid = ICE_TLV_ID_START; ice_dcb_cfg_to_lldp() local
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H A Dice_lib.c1 /* SPDX-License-Identifier: BSD-3-Clause */
270 * ice_map_bar - Map PCIe BAR memory
281 if (bar->res != NULL) { in ice_map_bar()
286 bar->rid = PCIR_BAR(bar_num); in ice_map_bar()
287 bar->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &bar->rid, in ice_map_bar()
289 if (!bar->res) { in ice_map_bar()
294 bar->tag = rman_get_bustag(bar->res); in ice_map_bar()
295 bar->handle = rman_get_bushandle(bar->res); in ice_map_bar()
296 bar->size = rman_get_size(bar->res); in ice_map_bar()
302 * ice_free_bar - Free PCIe BAR memory
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H A Dice_lib.h1 /* SPDX-License-Identifier: BSD-3-Clause */
83 * for_each_set_bit - For loop over each set bit in a bit string
94 (bit) != -1; \
125 /* global sysctl indicating whether to enable 5-layer scheduler topology */
145 /* Maximum TSO size is (256K)-1 */
146 #define ICE_TSO_SIZE ((256*1024) - 1)
154 #define ICE_MAX_DMA_SEG_SIZE ((16*1024) - 1)
199 (ice_is_bit_set(sc->feat_en, ICE_FEATURE_SAFE_MODE) ? ICE_SAFE_CAPS : ICE_FULL_CAPS)
238 * number assigned to it in hw->func_caps.guar_num_vsi, though there
248 #define ICE_MAX_MTU (ICE_MAX_FRAME_SIZE - \
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/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_fw_funcs.c2 * Copyright (c) 2017-2018 Cavium, Inc.
57 #define QM_PQ_SIZE_256B(pq_size) (pq_size ? DIV_ROUND_UP(pq_size, 0x100) - 1 : 0)
99 /* RL increment value - rate is specified in mbps. the factor of 1.01 was
121 #define QM_VP_RL_BYPASS_THRESH_SPEED (QM_VP_RL_UPPER_BOUND(10000) - 1)
135 …INES_VOQ0_RT_OFFSET + ext_voq * (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - PBF_REG_YCMD_QS_NUM_…
137 …RANTEED_VOQ0_RT_OFFSET + ext_voq * (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - PBF_REG_BTB_GUARANTE…
139 #define QM_VOQ_LINE_CRD(pbf_cmd_lines) ((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
146 /* Headroom per-port */
159 #define QM_STOP_CMD_PAUSE_MASK_MASK -1
188 …return NUM_OF_PHYS_TCS * (ECORE_IS_E5(p_hwfn->p_dev) ? MAX_NUM_PORTS_E5 : MAX_NUM_PORTS_BB) + port… in ecore_get_ext_voq()
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H A Decore_init_fw_funcs.h2 * Copyright (c) 2017-2018 Cavium, Inc.
36 * @brief ecore_qm_pf_mem_size - Prepare QM ILT sizes
41 * @param num_pf_cids - number of connections used by this PF
42 * @param num_vf_cids - number of connections used by VFs of this PF
43 * @param num_tids - number of tasks used by this PF
44 * @param num_pf_pqs - number of PQs used by this PF
45 * @param num_vf_pqs - number of PQs used by VFs of this PF
56 * @brief ecore_qm_common_rt_init - Prepare QM runtime init values for the
59 * @param p_hwfn - HW device data
60 * @param max_ports_per_engine - max number of ports per engine in HW
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H A Decore.h2 * Copyright (c) 2017-2018 Cavium, Inc.
146 ((sizeof(type_name) + (u32)(1<<(p_hwfn->p_dev->cache_shift))-1) & \
147 ~((1<<(p_hwfn->p_dev->cache_shift))-1))
164 PRINT_ERR((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
166 (p_dev)->name ? (p_dev)->name : "", \
172 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_NOTICE)) { \
173 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
175 (p_dev)->name ? (p_dev)->name : "", \
183 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_INFO)) { \
184 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \
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/freebsd/sys/dev/ixl/
H A Di40e_dcb.c3 Copyright (c) 2013-2018, Intel Corporation
70 u8 *buf = tlv->tlvinfo; in i40e_parse_ieee_etscfg_tlv()
71 u16 offset = 0; in i40e_parse_ieee_etscfg_tlv() local
76 * -------------------------- in i40e_parse_ieee_etscfg_tlv()
77 * |will-|CBS | Re- | Max | in i40e_parse_ieee_etscfg_tlv()
78 * |ing | |served| TCs | in i40e_parse_ieee_etscfg_tlv()
79 * -------------------------- in i40e_parse_ieee_etscfg_tlv()
82 etscfg = &dcbcfg->etscfg; in i40e_parse_ieee_etscfg_tlv()
83 etscfg->willing = (u8)((buf[offset] & I40E_IEEE_ETS_WILLING_MASK) >> in i40e_parse_ieee_etscfg_tlv()
85 etscfg->cbs = (u8)((buf[offset] & I40E_IEEE_ETS_CBS_MASK) >> in i40e_parse_ieee_etscfg_tlv()
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H A Di40e_common.c3 Copyright (c) 2013-2018, Intel Corporation
41 * i40e_set_mac_type - Sets MAC type
53 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { in i40e_set_mac_type()
54 switch (hw->device_id) { in i40e_set_mac_type()
75 hw->mac.type = I40E_MAC_XL710; in i40e_set_mac_type()
83 hw->mac.type = I40E_MAC_X722; in i40e_set_mac_type()
86 hw->mac.type = I40E_MAC_X722_VF; in i40e_set_mac_type()
91 hw->mac.type = I40E_MAC_VF; in i40e_set_mac_type()
94 hw->mac.type = I40E_MAC_GENERIC; in i40e_set_mac_type()
102 hw->mac.type, status); in i40e_set_mac_type()
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/freebsd/share/man/man4/
H A Dice.42 .\" SPDX-License-Identifier: BSD-3-Clause
4 .\" Copyright (c) 2019-2020, Intel Corporation
73 .Bl -bullet -compact
91 .Sx Link-Level Flow Control
113 .Sx Optics and auto-negotiation
115 .Sx PCI-Express Slot Bandwidth
236 To use RDMA monitoring, more MSI-X interrupts may need to be reserved.
241 .Bd -literal -offset indent
245 The number of extra MSI-X interrupt vectors may need to be adjusted.
248 .Bd -literal -offset indent
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/freebsd/libexec/bootpd/
H A Ddumptab.c2 * dumptab.c - handles dumping the database
50 #\tfirst field -- hostname (not indented)\n\ in dumptab()
51 #\tbf -- bootfile\n\ in dumptab()
52 #\tbs -- bootfile size in 512-octet blocks\n\ in dumptab()
53 #\tcs -- cookie servers\n\ in dumptab()
54 #\tdf -- dump file name\n\ in dumptab()
55 #\tdn -- domain name\n\ in dumptab()
56 #\tds -- domain name servers\n\ in dumptab()
57 #\tef -- extension file\n\ in dumptab()
58 #\tex -- exec file (YORK_EX_OPTION)\n\ in dumptab()
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/freebsd/sys/dev/ixgbe/
H A Dixgbe_82598.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
71 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
76 * than the 10ms recommended by the pci-e spec. To address this we need to
113 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
121 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_ops_82598()
122 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_ops_82598()
131 phy->ops.init = ixgbe_init_phy_ops_82598; in ixgbe_init_ops_82598()
134 mac->ops.start_hw = ixgbe_start_hw_82598; in ixgbe_init_ops_82598()
135 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_82598; in ixgbe_init_ops_82598()
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H A Dixgbe_common.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
61 u16 offset);
64 * ixgbe_init_ops_generic - Inits function ptrs
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_ops_generic()
72 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_ops_generic()
78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; in ixgbe_init_ops_generic()
81 eeprom->ops.read = ixgbe_read_eerd_generic; in ixgbe_init_ops_generic()
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom,rpmhpd.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
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H A Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
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H A Dqdu1000.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interconnect/qcom,icc.h>
11 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-sdx55.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interconnect/qcom,sdx55.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
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H A Dqcom-sdx65.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
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/freebsd/sys/cam/ctl/
H A Dctl_frontend_iscsi.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
95 &ping_timeout, 5, "Interval between ping (NOP-Out) requests, in seconds");
123 __func__, S->cs_initiator_addr, \
124 S->cs_initiator_name, ## __VA_ARGS__); \
132 S->cs_initiator_addr, \
133 S->cs_initiator_name, ## __VA_ARGS__); \
137 #define CFISCSI_SESSION_LOCK(X) mtx_lock(&X->cs_lock)
138 #define CFISCSI_SESSION_UNLOCK(X) mtx_unlock(&X->cs_lock)
139 #define CFISCSI_SESSION_LOCK_ASSERT(X) mtx_assert(&X->cs_lock, MA_OWNED)
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3566-lckfb-tspi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/soc/rockchip,vop2.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 compatible = "lckfb,tspi-rk3566", "rockchip,rk3566";
24 stdout-path = "serial2:1500000n8";
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/freebsd/contrib/file/
H A DChangeLog1 2024-11-27 14:44 Christos Zoulas <christos@zoulas.com>
6 2024-11-25 13:56 Christos Zoulas <christos@zoulas.com>
10 2024-11-10 13:56 Christos Zoulas <christos@zoulas.com>
14 offset that the "use" starts so that we don't double-count it.
17 2024-11-09 19:30 Christos Zoulas <christos@zoulas.com>
21 2024-11-02 14:34 Christos Zoulas <christos@zoulas.com>
25 2023-12-29 12:55 Christos Zoulas <christos@zoulas.com>
29 2023-07-29 12:55 Christos Zoulas <christos@zoulas.com>
33 2023-07-27 15:45 Christos Zoulas <christos@zoulas.com>
37 2023-07-17 11:53 Christos Zoulas <christos@zoulas.com>
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