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/linux/Documentation/networking/devlink/
H A Ddevlink-dpipe.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ``devlink-dpipe`` provides a standardized way to provide visibility into the
34 Level Path Compression trie (LPC-trie) in hardware.
36 In many situations trying to analyze systems failure solely based on the
45 The ``devlink-dpipe`` interface closes this gap. The hardware's pipeline is
50 configuration, but the ``devlink-dpipe`` interface uses it for visibility
52 ``devlink-dpipe`` should change according to the changes done by the
56 using Ternary Content Addressable Memory (TCAM). The TCAM memory can be
57 divided into TCAM regions. Complex TC filters can have multiple rules with
59 TCAM regions have a predefined lookup key. Offloading the TC filter rules
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/linux/Documentation/devicetree/bindings/arm/
H A Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_flex_pipe.c1 // SPDX-License-Identifier: GPL-2.0
77 * ice_sect_id - returns section ID
90 * ice_hw_ptype_ena - check if the PTYPE is enabled or not
97 test_bit(ptype, hw->hw_ptype); in ice_hw_ptype_ena()
112 * ice_gen_key_word - generate 16-bits of a key/mask word
120 * This function generates 16-bits from a 8-bit value, an 8-bit don't care mask
121 * and an 8-bit never match mask. The 16-bits of output are divided into 8 bits
133 * ------------------------------
145 return -EIO; in ice_gen_key_word()
150 /* encode the 8 bits into 8-bit key and 8-bit key invert */ in ice_gen_key_word()
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H A Dice_ddp.c1 // SPDX-License-Identifier: GPL-2.0
10 * boost tcam entries. The metadata labels names that match the following
27 * ice_verify_pkg - verify package
42 if (pkg->pkg_format_ver.major != ICE_PKG_FMT_VER_MAJ || in ice_verify_pkg()
43 pkg->pkg_format_ver.minor != ICE_PKG_FMT_VER_MNR || in ice_verify_pkg()
44 pkg->pkg_format_ver.update != ICE_PKG_FMT_VER_UPD || in ice_verify_pkg()
45 pkg->pkg_format_ver.draft != ICE_PKG_FMT_VER_DFT) in ice_verify_pkg()
49 seg_count = le32_to_cpu(pkg->seg_count); in ice_verify_pkg()
59 u32 off = le32_to_cpu(pkg->seg_offset[i]); in ice_verify_pkg()
69 if (len < off + le32_to_cpu(seg->seg_size)) in ice_verify_pkg()
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H A Dice_parser.c1 // SPDX-License-Identifier: GPL-2.0
12 * ice_parser_sect_item_get - parse an item from a section
73 if (index >= le16_to_cpu(hdr->count)) in ice_parser_sect_item_get()
80 * ice_parser_create_table - create an item table from a section
98 struct ice_seg *seg = hw->seg; in ice_parser_create_table()
103 return ERR_PTR(-EINVAL); in ice_parser_create_table()
107 return ERR_PTR(-ENOMEM); in ice_parser_create_table()
117 idx = le16_to_cpu(hdr->offset) + in ice_parser_create_table()
137 dev_info(dev, "\talu0 = %d\n", bm->alu0); in ice_imem_bst_bm_dump()
138 dev_info(dev, "\talu1 = %d\n", bm->alu1); in ice_imem_bst_bm_dump()
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H A Dice_vlan_mode.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2019-2021, Intel Corporation. */
7 * ice_pkg_get_supported_vlan_mode - determine if DDP supports Double VLAN mode
26 return -ENOMEM; in ice_pkg_get_supported_vlan_mode()
29 sect->count = cpu_to_le16(1); in ice_pkg_get_supported_vlan_mode()
30 sect->offset = cpu_to_le16(ICE_META_VLAN_MODE_ENTRY); in ice_pkg_get_supported_vlan_mode()
42 arr[i] = le32_to_cpu(sect->entry.bm[i]); in ice_pkg_get_supported_vlan_mode()
56 * ice_aq_get_vlan_mode - get the VLAN mode of the device
58 * @get_params: structure FW fills in based on the current VLAN mode config
69 return -EINVAL; in ice_aq_get_vlan_mode()
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/linux/drivers/net/ethernet/mscc/
H A Docelot_vcap.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
23 VCAP_CMD_WRITE = 0, /* Copy from Cache to TCAM */
24 VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */
40 u32 tg_sw; /* Current type-group */
45 u32 tg_value; /* Current type-group value */
46 u32 tg_mask; /* Current type-group mask */
52 return ocelot_target_read(ocelot, vcap->target, VCAP_CORE_UPDATE_CTRL); in vcap_read_update_ctrl()
62 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap->entry_count) in vcap_cmd()
74 ocelot_target_write(ocelot, vcap->target, value, VCAP_CORE_UPDATE_CTRL); in vcap_cmd()
81 /* Convert from 0-based row to VCAP entry row and run command */
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H A Docelot.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
30 /* Caller must hold &ocelot->mact_lock */
36 /* Caller must hold &ocelot->mact_lock */
48 /* Caller must hold &ocelot->mact_lock */
90 if (mc_ports & BIT(ocelot->num_phys_ports)) in __ocelot_mact_learn()
109 mutex_lock(&ocelot->mact_lock); in ocelot_mact_learn()
111 mutex_unlock(&ocelot->mact_lock); in ocelot_mact_learn()
122 mutex_lock(&ocelot->mact_lock); in ocelot_mact_forget()
133 mutex_unlock(&ocelot->mact_lock); in ocelot_mact_forget()
145 mutex_lock(&ocelot->mact_lock); in ocelot_mact_lookup()
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/linux/net/dsa/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 tristate "No-op tag driver"
28 tristate "Tag driver for Atheros AR9331 SoC with built-in switch"
31 the Atheros AR9331 SoC with built-in switch.
38 tristate "Tag driver for Broadcom switches using in-frame headers"
45 tristate "Tag driver for Broadcom legacy switches using in-frame headers"
108 hardware-defined injection/extraction frame header. Flow control
116 custom VLAN-based header. Frames that require timestamping, such as
117 PTP, are not delivered over Ethernet but over register-based MMIO.
119 this mode, less TCAM resources (VCAP IS1, IS2, ES0) are available for
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H A Dtag_ocelot_8021q.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2020-2021 NXP
4 * An implementation of the software-defined tag_8021q.c tagger format, which
6 * this by using the TCAM engines for:
7 * - pushing the RX VLAN as a second, outer tag, on egress towards the CPU port
8 * - redirecting towards the correct front port based on TX VLAN and popping
17 #define OCELOT_8021Q_NAME "ocelot-8021q"
27 struct ocelot_8021q_tagger_private *priv = dp->ds->tagger_data; in ocelot_defer_xmit()
28 struct ocelot_8021q_tagger_data *data = &priv->data; in ocelot_defer_xmit()
33 xmit_work_fn = data->xmit_work_fn; in ocelot_defer_xmit()
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H A Dtag_8021q.c1 // SPDX-License-Identifier: GPL-2.0
15 /* Binary structure of the fake 12-bit VID field (when the TPID is
19 * +-----------+-----+-----------------+-----------+-----------------------+
21 * +-----------+-----+-----------------+-----------+-----------------------+
23 * RSV - VID[11:10]:
26 * SWITCH_ID - VID[8:6]:
29 * VBID - { VID[9], VID[5:4] }:
34 * PORT - VID[3:0]:
94 return DSA_8021Q_RSV | DSA_8021Q_SWITCH_ID(dp->ds->index) | in dsa_tag_8021q_standalone_vid()
95 DSA_8021Q_PORT(dp->index); in dsa_tag_8021q_standalone_vid()
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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dinterlaken-lac.txt2 Freescale Interlaken Look-Aside Controller Device Bindings
6 - Interlaken Look-Aside Controller (LAC) Node
7 - Example LAC Node
8 - Interlaken Look-Aside Controller (LAC) Software Portal Node
9 - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
10 - Example LAC SWP Node with Child Nodes
13 Interlaken Look-Aside Controller (LAC) Node
17 The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
18 facilitate interoperability between a data path device and a look-aside
19 co-processor, the Interlaken Look-Aside protocol is defined for short
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/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpni.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2016 Freescale Semiconductor Inc.
20 * DPNI_MAX_TC - Maximum number of traffic classes
24 * DPNI_MAX_DPBP - Maximum number of buffer pools per DPNI
29 * DPNI_ALL_TCS - All traffic classes considered; see dpni_set_queue()
31 #define DPNI_ALL_TCS (u8)(-1)
33 * DPNI_ALL_TC_FLOWS - All flows within traffic class considered; see
36 #define DPNI_ALL_TC_FLOWS (u16)(-1)
38 * DPNI_NEW_FLOW_ID - Generate new flow ID; see dpni_set_queue()
40 #define DPNI_NEW_FLOW_ID (u16)(-1)
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/linux/drivers/net/ethernet/meta/fbnic/
H A Dfbnic_csr.h1 /* SPDX-License-Identifier: GPL-2.0 */
110 (FBNIC_BD_DESC_ADDR_MASK & ~(FBNIC_BD_DESC_ADDR_MASK - 1))
137 #define FBNIC_RCD_AL_BUFF_FRAG_MASK (FBNIC_BD_FRAG_COUNT - 1)
635 (FBNIC_RPC_RSS_KEY_DWORD_LEN - 1)
638 FBNIC_RPC_RSS_KEY_DWORD_LEN * 32 - \
661 /* TCAM Tables */
664 /* 64 Action TCAM Entries, 12 registers
929 #define FBNIC_CSR_END_QUEUE (0x40000 + 0x400 * FBNIC_MAX_QUEUES - 1)
975 * have to do the math and determine the offset based on the mailbox
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_filter.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
65 return -ENOMEM; in set_tcb_field()
69 req->reply_ctrl = htons(REPLY_CHAN_V(0) | in set_tcb_field()
70 QUEUENO_V(adap->sge.fw_evtq.abs_id) | in set_tcb_field()
72 req->word_cookie = htons(TCB_WORD_V(word) | TCB_COOKIE_V(ftid)); in set_tcb_field()
73 req->mask = cpu_to_be64(mask); in set_tcb_field()
74 req->val = cpu_to_be64(val); in set_tcb_field()
75 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3); in set_tcb_field()
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H A Dcxgb4_main.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
126 #define FW4_CFNAME "cxgb4/t4-config.txt"
127 #define FW5_CFNAME "cxgb4/t5-config.txt"
128 #define FW6_CFNAME "cxgb4/t6-config.txt"
144 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
154 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
158 * offset by 2 bytes in order to have the IP headers line up on 4-byte
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H A Dt4_hw.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 * t4_wait_op_done_val - wait until an operation is completed
46 * @mask: a single-bit field within @reg that indicates completion
55 * operation completes and -EAGAIN otherwise.
68 if (--attempts == 0) in t4_wait_op_done_val()
69 return -EAGAIN; in t4_wait_op_done_val()
83 * t4_set_reg_field - set a register field to a value
102 * t4_read_indirect - read indirectly addressed registers
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/linux/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dcxgb4vf_main.c2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 #include <linux/dma-mapping.h>
74 * order MSI-X then MSI. This parameter determines which of these schemes the
77 * msi = 2: choose from among MSI-X and MSI
82 * the PCI-E SR-IOV standard).
91 MODULE_PARM_DESC(msi, "whether to use MSI-X or MSI");
112 * list entries are 64-bit PCI DMA addresses. And since the state of
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/linux/drivers/net/dsa/sja1105/
H A Dsja1105_dynamic_config.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
6 /* In the dynamic configuration interface, the switch exposes a register-like
13 * This file creates a per-switch-family abstraction called
15 * - sja1105_dynamic_config_write
16 * - sja1105_dynamic_config_read
25 * +-----------------------------------------+------------------+
27 * +-----------------------------------------+------------------+
29 * <----------------------- packed_size ------------------------>
33 * function is reused (bar exceptional cases - see
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H A Dsja1105_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
76 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; in sja1105_is_vlan_configured()
77 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count; in sja1105_is_vlan_configured()
84 return -1; in sja1105_is_vlan_configured()
89 struct sja1105_private *priv = ds->priv; in sja1105_drop_untagged()
92 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_drop_untagged()
107 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_pvid_apply()
122 struct sja1105_private *priv = ds->priv; in sja1105_commit_pvid()
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux/drivers/scsi/csiostor/
H A Dcsio_hw.c4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
64 {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"},
65 {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"},
66 {"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"},
67 {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"},
68 {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"},
69 {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"},
70 {"T540-CH 10G", "Chelsio T540-CH 10G [FCoE]"},
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/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
326 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 },
327 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 },
328 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 },
329 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
330 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 },
331 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 },
332 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 },
333 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 },
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